J-11 chip set - Revision history

Jnc: /* External links */ Standardize URLs

2026-10-08T22:03:49Z

External links: Standardize URLs

← Older revision		Revision as of 22:03, 8 October 2026
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	* [http://www.bitsavers.org/pdf/dec/pdp11/1173/EK-DCJ11-UG-PRE_J11ug_Oct83.pdf DCJ11 Microprocessor User's Guide] (EK-DCJ11-UG-PRE]		* [http://www.bitsavers.org/pdf/dec/pdp11/1173/EK-DCJ11-UG-PRE_J11ug_Oct83.pdf DCJ11 Microprocessor User's Guide] (EK-DCJ11-UG-PRE]
	* [~~https~~://bitsavers.org/pdf/dec/pdp11/j11/J-11_Programmers_Reference_Jan82.pdf J-11 Programmer's Reference]		* [http://bitsavers.org/pdf/dec/pdp11/j11/J-11_Programmers_Reference_Jan82.pdf J-11 Programmer's Reference]
	* [~~https~~://bitsavers.org/pdf/dec/pdp11/j11/J-11_Control_Chip_Specification_Jun82.pdf J-11 Control Chip Specification]		* [http://bitsavers.org/pdf/dec/pdp11/j11/J-11_Control_Chip_Specification_Jun82.pdf J-11 Control Chip Specification]
	* [~~https~~://bitsavers.org/pdf/dec/pdp11/j11/J-11_Data_Chip_Specification_Jul82.pdf J-11 Data Chip Specification]		* [http://bitsavers.org/pdf/dec/pdp11/j11/J-11_Data_Chip_Specification_Jul82.pdf J-11 Data Chip Specification]
	* [http://www.bitsavers.org/pdf/dec/internal/Semiconductor_Handbook_V1_1987.pdf DEC Semiconductor Databook, Volume 1], pp. 261-334		* [http://www.bitsavers.org/pdf/dec/internal/Semiconductor_Handbook_V1_1987.pdf DEC Semiconductor Databook, Volume 1], pp. 261-334
	* [http://simh.trailing-edge.com/semi/j11.html J-11 (1983)]		* [http://simh.trailing-edge.com/semi/j11.html J-11 (1983)]

Jnc: /* External links */ +PDP-11/HACK

2025-04-18T22:45:50Z

External links: +PDP-11/HACK

← Older revision		Revision as of 22:45, 18 April 2025
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	* [http://simh.trailing-edge.com/semi/j11.html J-11 (1983)]		* [http://simh.trailing-edge.com/semi/j11.html J-11 (1983)]
	** [http://simh.trailing-edge.com/semi/ucode/j11/j11.mcr J-11 microcode]		** [http://simh.trailing-edge.com/semi/ucode/j11/j11.mcr J-11 microcode]
			* [http://madrona.ca/e/pdp11hack/index.html PDP-11/HACK] - use of a J-11 in a vintage experiment

	[[Category: PDP-11 Processors]]		[[Category: PDP-11 Processors]]

Jnc: /* External links */ +J-11 Programmer's Reference

2024-02-29T21:19:19Z

External links: +J-11 Programmer's Reference

← Older revision		Revision as of 21:19, 29 February 2024
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	* [http://www.bitsavers.org/pdf/dec/pdp11/1173/EK-DCJ11-UG-PRE_J11ug_Oct83.pdf DCJ11 Microprocessor User's Guide] (EK-DCJ11-UG-PRE]		* [http://www.bitsavers.org/pdf/dec/pdp11/1173/EK-DCJ11-UG-PRE_J11ug_Oct83.pdf DCJ11 Microprocessor User's Guide] (EK-DCJ11-UG-PRE]
			* [https://bitsavers.org/pdf/dec/pdp11/j11/J-11_Programmers_Reference_Jan82.pdf J-11 Programmer's Reference]
			* [https://bitsavers.org/pdf/dec/pdp11/j11/J-11_Control_Chip_Specification_Jun82.pdf J-11 Control Chip Specification]
			* [https://bitsavers.org/pdf/dec/pdp11/j11/J-11_Data_Chip_Specification_Jul82.pdf J-11 Data Chip Specification]
	* [http://www.bitsavers.org/pdf/dec/internal/Semiconductor_Handbook_V1_1987.pdf DEC Semiconductor Databook, Volume 1], pp. 261-334		* [http://www.bitsavers.org/pdf/dec/internal/Semiconductor_Handbook_V1_1987.pdf DEC Semiconductor Databook, Volume 1], pp. 261-334
	* [http://simh.trailing-edge.com/semi/j11.html J-11 (1983)]		* [http://simh.trailing-edge.com/semi/j11.html J-11 (1983)]

Jnc: /* External links */ +J-11 microcode

2022-03-28T21:40:57Z

External links: +J-11 microcode

← Older revision		Revision as of 21:40, 28 March 2022
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	* [http://www.bitsavers.org/pdf/dec/internal/Semiconductor_Handbook_V1_1987.pdf DEC Semiconductor Databook, Volume 1], pp. 261-334		* [http://www.bitsavers.org/pdf/dec/internal/Semiconductor_Handbook_V1_1987.pdf DEC Semiconductor Databook, Volume 1], pp. 261-334
	* [http://simh.trailing-edge.com/semi/j11.html J-11 (1983)]		* [http://simh.trailing-edge.com/semi/j11.html J-11 (1983)]
			** [http://simh.trailing-edge.com/semi/ucode/j11/j11.mcr J-11 microcode]

	[[Category: PDP-11 Processors]]		[[Category: PDP-11 Processors]]

Jnc: /* External links */ +EK-DCJ11-UG-PRE

2022-03-10T14:27:16Z

External links: +EK-DCJ11-UG-PRE

← Older revision		Revision as of 14:27, 10 March 2022
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	==External links==		==External links==

			* [http://www.bitsavers.org/pdf/dec/pdp11/1173/EK-DCJ11-UG-PRE_J11ug_Oct83.pdf DCJ11 Microprocessor User's Guide] (EK-DCJ11-UG-PRE]
	* [http://www.bitsavers.org/pdf/dec/internal/Semiconductor_Handbook_V1_1987.pdf DEC Semiconductor Databook, Volume 1], pp. 261-334		* [http://www.bitsavers.org/pdf/dec/internal/Semiconductor_Handbook_V1_1987.pdf DEC Semiconductor Databook, Volume 1], pp. 261-334
	* [http://simh.trailing-edge.com/semi/j11.html J-11 (1983)]		* [http://simh.trailing-edge.com/semi/j11.html J-11 (1983)]

	~~{{PDP-11}}~~

	[[Category: PDP-11 Processors]]		[[Category: PDP-11 Processors]]

Jnc: /* External links */ spec in DEC Semiconductor Databook

2021-03-29T00:51:37Z

External links: spec in DEC Semiconductor Databook

← Older revision		Revision as of 00:51, 29 March 2021
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	Most uses on DEC PDP-11 [[Central Processing Unit\|CPU]] boards (all for the [[QBUS]]) contain an external [[cache]].		Most uses on DEC PDP-11 [[Central Processing Unit\|CPU]] boards (all for the [[QBUS]]) contain an external [[cache]].

	==External ~~link~~==		==External links==

			* [http://www.bitsavers.org/pdf/dec/internal/Semiconductor_Handbook_V1_1987.pdf DEC Semiconductor Databook, Volume 1], pp. 261-334
	* [http://simh.trailing-edge.com/semi/j11.html J-11 (1983)]		* [http://simh.trailing-edge.com/semi/j11.html J-11 (1983)]

Jnc: +link

2020-01-05T20:31:59Z

+link

← Older revision		Revision as of 20:31, 5 January 2020
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	The '''J-11''' (formally, the '''DCJ11''', although DEC documentation uses both names) is a high-performance [[Metal Oxide Semiconductor\|CMOS]] implementation of the [[PDP-11 architecture]], used in both the [[KDJ11 CPUs]], and a variety of peripherals. It was implemented in two [[integrated circuit\|chips]] ('Control' and 'Data') carried on a single 60-pin [[Dual Inline Package\|DIP]] carrier.		The '''J-11''' (formally, the '''DCJ11''', although DEC documentation uses both names) is a high-performance [[Metal Oxide Semiconductor\|CMOS]] implementation of the [[PDP-11 architecture]], used in both the [[KDJ11 CPUs]], and a variety of peripherals. It was implemented in two [[integrated circuit\|chips]] ('Control' and 'Data') carried on a single 60-pin [[Dual Inline Package\|DIP]] carrier.

	It implements the full [[PDP-11 Memory Management]] architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in [[FP11 floating point\|FP11]] [[floating point]] support (using [[microcode]]), it can operate with an [[FPJ11]] floating point accelerator chip for higher performance.		It implements the full [[PDP-11 Memory Management]] architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in [[FP11 floating point\|FP11]] [[floating point]] support (using [[microcode]]), it can operate with an optional [[FPJ11 floating point accelerator]] [[integrated circuit\|chip]] for higher performance.

	Most uses on DEC PDP-11 [[Central Processing Unit\|CPU]] boards (all for the [[QBUS]]) contain an external [[cache]].		Most uses on DEC PDP-11 [[Central Processing Unit\|CPU]] boards (all for the [[QBUS]]) contain an external [[cache]].

Jnc: avoid dab, clarify

2019-09-17T13:06:57Z

avoid dab, clarify

← Older revision		Revision as of 13:06, 17 September 2019
Line 3:		Line 3:
	The '''J-11''' (formally, the '''DCJ11''', although DEC documentation uses both names) is a high-performance [[Metal Oxide Semiconductor\|CMOS]] implementation of the [[PDP-11 architecture]], used in both the [[KDJ11 CPUs]], and a variety of peripherals. It was implemented in two [[integrated circuit\|chips]] ('Control' and 'Data') carried on a single 60-pin [[Dual Inline Package\|DIP]] carrier.		The '''J-11''' (formally, the '''DCJ11''', although DEC documentation uses both names) is a high-performance [[Metal Oxide Semiconductor\|CMOS]] implementation of the [[PDP-11 architecture]], used in both the [[KDJ11 CPUs]], and a variety of peripherals. It was implemented in two [[integrated circuit\|chips]] ('Control' and 'Data') carried on a single 60-pin [[Dual Inline Package\|DIP]] carrier.

	It implements the full [[PDP-11 Memory Management]] architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in [[FP11]] [[floating point]] support (using [[microcode]]), it can operate with an [[FPJ11]] floating point accelerator chip.		It implements the full [[PDP-11 Memory Management]] architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in [[FP11 floating point\|FP11]] [[floating point]] support (using [[microcode]]), it can operate with an [[FPJ11]] floating point accelerator chip for higher performance.

	Most uses on DEC PDP-11 [[Central Processing Unit\|CPU]] boards (all for the [[QBUS]]) contain an external [[cache]].		Most uses on DEC PDP-11 [[Central Processing Unit\|CPU]] boards (all for the [[QBUS]]) contain an external [[cache]].

Jnc: +link to J11 page

2018-07-15T15:58:18Z

+link to J11 page

← Older revision		Revision as of 15:58, 15 July 2018
Line 6:		Line 6:

	Most uses on DEC PDP-11 [[Central Processing Unit\|CPU]] boards (all for the [[QBUS]]) contain an external [[cache]].		Most uses on DEC PDP-11 [[Central Processing Unit\|CPU]] boards (all for the [[QBUS]]) contain an external [[cache]].

			==External link==

			* [http://simh.trailing-edge.com/semi/j11.html J-11 (1983)]

	{{PDP-11}}		{{PDP-11}}

	[[Category: PDP-11 Processors]]		[[Category: PDP-11 Processors]]

Jnc: Proper cat

2018-02-17T20:40:10Z

Proper cat

← Older revision		Revision as of 20:40, 17 February 2018
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	{{PDP-11}}		{{PDP-11}}

	[[Category: PDP-~~11s]]~~		[[Category: PDP-11 Processors]]
	~~[[Category: DEC~~ Processors]]

← Older revision		Revision as of 20:31, 5 January 2020
Line 3:		Line 3:
	The '''J-11''' (formally, the '''DCJ11''', although DEC documentation uses both names) is a high-performance [[Metal Oxide Semiconductor\|CMOS]] implementation of the [[PDP-11 architecture]], used in both the [[KDJ11 CPUs]], and a variety of peripherals. It was implemented in two [[integrated circuit\|chips]] ('Control' and 'Data') carried on a single 60-pin [[Dual Inline Package\|DIP]] carrier.		The '''J-11''' (formally, the '''DCJ11''', although DEC documentation uses both names) is a high-performance [[Metal Oxide Semiconductor\|CMOS]] implementation of the [[PDP-11 architecture]], used in both the [[KDJ11 CPUs]], and a variety of peripherals. It was implemented in two [[integrated circuit\|chips]] ('Control' and 'Data') carried on a single 60-pin [[Dual Inline Package\|DIP]] carrier.

	It implements the full [[PDP-11 Memory Management]] architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in [[FP11 floating point\|FP11]] [[floating point]] support (using [[microcode]]), it can operate with an [[FPJ11]] floating point accelerator chip for higher performance.		It implements the full [[PDP-11 Memory Management]] architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in [[FP11 floating point\|FP11]] [[floating point]] support (using [[microcode]]), it can operate with an optional [[FPJ11 floating point accelerator]] [[integrated circuit\|chip]] for higher performance.

	Most uses on DEC PDP-11 [[Central Processing Unit\|CPU]] boards (all for the [[QBUS]]) contain an external [[cache]].		Most uses on DEC PDP-11 [[Central Processing Unit\|CPU]] boards (all for the [[QBUS]]) contain an external [[cache]].