KA10 - Revision history

Jnc: /* External links */ trim URL

2025-04-22T17:50:24Z

‎External links: trim URL

2025-04-22T12:43:58Z

‎External link: +one from Paul Allen's collection at the LCM

2023-09-06T05:28:29Z

Unredirect ITS.

2022-08-10T11:04:31Z

use new inst speed

2022-01-09T20:49:05Z

+backplanes; +See also, Ext links

2018-11-22T17:56:52Z

better image layout

2018-11-22T16:57:25Z

Add fonr panel image

2018-02-17T20:44:32Z

Proper cat

2018-01-08T13:42:43Z

Move system pic to top

2018-01-08T10:27:00Z

@@ Line 44: / Line 44: @@
 * [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V1_Oct74.pdf PDP-10 module schematics Vol.1]
 * [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V2_Oct74.pdf PDP-10 module schematics Vol.2]
-* [https://onlineonly.christies.com/s/firsts-history-computing-paul-g-allen-collection/dec-pdp-10-ka10-mainframe-computer-112/230050?ldp_breadcrumb=back DEC PDP-10 KA10 mainframe computer] - one from [[Paul Allen]]'s collection at the [[Living Computer Museum|LCM]], includes several images
+* [https://onlineonly.christies.com/s/firsts-history-computing-paul-g-allen-collection/dec-pdp-10-ka10-mainframe-computer-112/230050 DEC PDP-10 KA10 mainframe computer] - one from [[Paul Allen]]'s collection at the [[Living Computer Museum|LCM]], includes several images
 [[Category: PDP-10 Processors]]

@@ Line 32: / Line 32: @@
 It was also the machine on which the [[Incompatible Timesharing System|ITS]] and [[TENEX]] [[operating system]]s were developed, after the machines were modified to provide [[virtual memory|paging]].
 ==See also==
@@ Line 43: / Line 44: @@
 * [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V1_Oct74.pdf PDP-10 module schematics Vol.1]
 * [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V2_Oct74.pdf PDP-10 module schematics Vol.2]
 [[Category: PDP-10 Processors]]

@@ Line 30: / Line 30: @@
 [[Image:KA10 mod end.jpg|150px|thumb|left|B-series FLIP CHIP used in the KA10 CPU]]
-It was also the machine on which the [[ITS]] and [[TENEX]] [[operating system]]s were developed, after the machines were modified to provide [[virtual memory|paging]].
+It was also the machine on which the [[Incompatible Timesharing System|ITS]] and [[TENEX]] [[operating system]]s were developed, after the machines were modified to provide [[virtual memory|paging]].
 ==See also==

@@ Line 12: / Line 12: @@
 | virtual address = 18 bits
 | logic type = silicon [[transistor]]s and diodes
-| design type =  asynchronous with hardware subroutines
+| design type = asynchronous with hardware subroutines
-| clock speed = 3 μsec (approximately - different instructions take different amounts of time, the CPU is not synchronous)
+| instruction speed = 3 μsec (approximately - different instructions take different amounts of time, the CPU is not synchronous)
 | memory speed = 1.0 μsec (fast), 1.8 μsec (slow)
 | memory mgmt = dual [[base and bounds]] register pairs (non-customized machines)

@@ Line 21: / Line 21: @@
 | price = US$150K (CPU), US$300-700K (system)
 }}
 [[Image:KA10 mod end.jpg|150px|thumb|left|B-series FLIP CHIP used in the KA10 CPU]]
-The '''KA10''' was the first generation of [[PDP-10]] [[Central Processing Unit|processors]] (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of discrete transistors, on [[DEC card form factor|short single]] [[FLIP CHIP]] cards.
+It was also the machine on which the [[ITS]] and [[TENEX]] [[operating system]]s were developed, after the machines were modified to provide [[virtual memory|paging]].
-It had hardware support for [[time-sharing]] (two modes, 'User' and 'Executive'), as well as [[base and bounds]] memory management hardware. These were used in the first [[DECsystem-10]] models, running [[TOPS-10]].
+==See also==
-It was also the machine on which the [[ITS]] and [[TENEX]] [[operating system]]s were developed, after the machines were modified to provide [[paging]].
+* [[KI10]]
-[[Image:KA10FrontPanel.jpg|thumb|left|300px|The front panel of a KA10]]
+==External links==
 [[Category: PDP-10 Processors]]

@@ Line 1: / Line 1: @@
 {{Infobox Machine
 | name = KA10
 | manufacturer = [[Digital Equipment Corporation]]
 | architecture = [[PDP-10]]
@@ Line 20: / Line 22: @@
 }}
-[[Image:ka10.jpg|thumb|left|KA10-based PDP-10 system]]
+[[Image:KA10 mod end.jpg|150px|thumb|right|B-series FLIP CHIP used in the KA10 CPU]]
 The '''KA10''' was the first generation of [[PDP-10]] [[Central Processing Unit|processors]] (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of discrete transistors, on [[DEC card form factor|short single]] [[FLIP CHIP]] cards.
-[[Image:KA10 mod end.jpg|150px|thumb|left|B-series FLIP CHIP used in the KA10 CPU]]
+It had hardware support for [[time-sharing]] (two modes, 'User' and 'Executive'), as well as [[base and bounds]] memory management hardware. These were used in the first [[DECsystem-10]] models, running [[TOPS-10]].
-It had hardware support for [[time-sharing]] (two modes, 'User' and 'Executive'), as well as [[base and bounds]] memory management hardware. These were used in the first [[DECsystem-10]] models, running [[TOPS-10]].
+[[Image:KA10FrontPanel.jpg|thumb|left|300px|The front panel of a KA10]]
 It was also the machine on which the [[ITS]] and [[TENEX]] [[operating system]]s were developed, after the machines were modified to provide [[paging]].
 [[Category: PDP-10 Processors]]

← Older revision		Revision as of 20:44, 17 February 2018
Line 30:		Line 30:
	It was also the machine on which the [[ITS]] and [[TENEX]] [[operating system]]s were developed, after the machines were modified to provide [[paging]].		It was also the machine on which the [[ITS]] and [[TENEX]] [[operating system]]s were developed, after the machines were modified to provide [[paging]].

−	[[Category:~~DEC CPUs~~]]	+	[[Category: PDP-10 Processors]]

@@ Line 28: / Line 28: @@
 It was also the machine on which the [[ITS]] and [[TENEX]] [[operating system]]s were developed, after the machines were modified to provide [[paging]].
-[[Image:ka10.jpg|thumb|right|PDP-10 system.]]
+[[Image:ka10.jpg|thumb|left|PDP-10 system.]]
 [[Category:DEC CPUs]]