KA11 CPU - Revision history

Jnc: /* External links */ +KA11 versions of PDP-11/20 modules

2025-08-08T06:10:13Z

‎External links: +KA11 versions of PDP-11/20 modules

2024-10-11T21:42:53Z

‎Implementation: Improve diagram visuals a bit

2024-02-29T21:10:49Z

‎See also: KY11-A Programmer's Console

2023-07-05T23:44:52Z

minor clarification

2023-05-16T18:08:17Z

‎External links: +Details of Design, KA11

2022-12-05T17:15:31Z

‎External links: +engineering drawings

2022-11-04T16:19:25Z

‎Data paths: clarify desc; better img loc

2022-11-04T16:16:57Z

+ latching mux circ diag

2022-11-04T16:02:03Z

‎External links: +KA11 Design Critique

2022-10-11T10:30:47Z

‎External links: Narrow down category.

@@ Line 139: / Line 139: @@
 ==External links==
-* [http://www.bitsavers.org/pdf/dec/pdp11/1120/KA11_ProcessorMan.pdf KA11 processor manual]
+* [http://www.bitsavers.org/pdf/dec/pdp11/1120/ 11/20] - documentation at [[Bitsavers]] is here
-* [http://www.bitsavers.org/pdf/dec/pdp11/1120/1120_SystemSchems_Feb70.pdf PDP-11/20 engineering drawings] - KA11 on pp. 3-58 of the PDF; block diagram on pg. 12
+** [http://www.bitsavers.org/pdf/dec/pdp11/1120/KA11_ProcessorMan.pdf KA11 processor manual]
 * [http://www.bitsavers.org/pdf/dec/pdp11/memos/690904_Details_of_Design_KA11.pdf Details of Design, KA11] - early memo explaining internal operation
 * [http://www.bitsavers.org/pdf/dec/pdp11/memos/691023_KA11_Design_Critique.pdf KA11 Design Critique] - a retrospective memo as the machine was going into production
 [[Category: PDP-11 UNIBUS Processors]]

@@ Line 105: / Line 105: @@
 ! !! colspan="6" | Connector
 |-
-! Slot !! A !! B !! C !! D !! E !! F
+! Slot !! A !! B !! &nbsp; C &nbsp; !! &nbsp; D &nbsp; !! &nbsp; E &nbsp; !! &nbsp; F &nbsp;
 |-
 | 1 || colspan="6" style="text-align:center;" | [[KY11-A Programmer's Console|KY11-A]]

@@ Line 34: / Line 34: @@
 Each major state contains a number of minor states, as needed to perform the operations of that state (e.g. perform a bus cycle to fetch a memory word). These minor states are named ISRn (from Instruction Shift Register) for minor states associated with internal processor actions, and BSRn (from Bus Shift Register) for minor states associated with bus operations.
-Not all instructions pass through all 5 major states, although all do pass through 'Fetch'. 'Source' and 'Destination' are not entered if the [[PDP-11 architecture#Addressing modes|mode]] for that operand is 'Register'; only 'full' double-operand instructions (i.e. those with mode bits in the source) will enter 'Source' state.
+Not all instructions pass through all 5 major states, although all do pass through 'Fetch'. 'Source' and 'Destination' are not entered if the [[PDP-11 architecture#Addressing modes|mode]] for that operand is 'Register'; only 'full' double-operand instructions (i.e. those with non-zero mode bits in the source) will enter 'Source' state.
 'Source' and 'Destination' are very similar, but within each, the sequence of minor states varies considerably between each of the seven [[PDP-11 architecture#Addressing modes|operand modes]] other than mode 0, direct register access (for which, as previously mentioned, the Source or Destination major state is bypassed entirely).

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 * [http://www.bitsavers.org/pdf/dec/pdp11/1120/KA11_ProcessorMan.pdf KA11 processor manual]
 * [http://www.bitsavers.org/pdf/dec/pdp11/1120/1120_SystemSchems_Feb70.pdf PDP-11/20 engineering drawings] - KA11 on pp. 3-58 of the PDF; block diagram on pg. 12
-* [http://www.bitsavers.org/pdf/dec/pdp11/memos/691023_KA11_Design_Critique.pdf KA11 Design Critique]
+* [http://www.bitsavers.org/pdf/dec/pdp11/memos/690904_Details_of_Design_KA11.pdf Details of Design, KA11] - early memo explaining internal operation
 [[Category: PDP-11 UNIBUS Processors]]

@@ Line 39: / Line 39: @@
 ===Data paths===
 [[Image:LatchingMux.jpg|thumb|left|200px|Latching mux]]
-The [[arithmetic logic unit|ALU]] in the KA11 is an extremely simple one, unlike all other -11's; it can only perform additions.
+Each input to the adder has a three-input mux (implemented as a NOR [[gate]] of three inputs with NANDs to enable them; shown to the side); a latch formed with the output of the mux can also be fed back through the mux (i.e. as a fourth input to it). The A mux can select from register data, and complemented register and bus data; the B mux can select register and bus data.
 Enabling two inputs to a mux ORs together the data in the two inputs. To perform an AND, De Morgan's theorem is used; the complemented data inputs are ORed together, and the result is again complemented; this, however, requires two passes through the ALU.

@@ Line 1: / Line 1: @@
 [[Image:KA11FrontPanel.jpg|right|thumb|300px|KA11 [[front panel]]]]
-The '''KA11''' is the [[Central Processing Unit|CPU]] of the [[PDP-11/20]], the first [[PDP-11]].
+The '''KA11''' is the [[Central Processing Unit|CPU]] of the [[PDP-11/20]], the first [[PDP-11]]. It was the only PDP-11 CPU which was not [[microcode]]d (since the cheap [[read-only memory|ROMs]] which make micro-programming cost-effective in smaller machines were not available at the time it was designed).
 The KA11 was implemented as a set of [[DEC card form factor|extended length]] [[FLIP CHIP]]s, containing early [[74 series]] [[transistor-transistor logic|TTL]] chips. They all plugged into a custom [[backplane]], formed from three 4-slot [[system unit]]s wired together into one monolithic unit.
 ==Internal structure==
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 * [http://www.bitsavers.org/pdf/dec/pdp11/1120/KA11_ProcessorMan.pdf KA11 processor manual]
+* [http://www.bitsavers.org/pdf/dec/pdp11/memos/691023_KA11_Design_Critique.pdf KA11 Design Critique]
 [[Category: PDP-11 UNIBUS Processors]]

← Older revision		Revision as of 10:30, 11 October 2022
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	{{PDP-11}}		{{PDP-11}}

−	[[Category: PDP-11 ~~Processors]]~~	+	[[Category: PDP-11 UNIBUS Processors]]
−	~~[[Category:~~ UNIBUS Processors]]