KA750 CPU - Revision history

Jnc: /* External links */ +PCS Module FMPS

2024-05-18T01:33:20Z

‎External links: +PCS Module FMPS

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‎External links: +board images

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typos

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‎Components: +Remote Diagnostic Module subsys id

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+Backplane details

Jnc: Move impl technology to main 750 article; add PCS

2022-06-03T17:47:15Z

Move impl technology to main 750 article; add PCS

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+750 block diag

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Expand considerably

Jnc: Stubby, but a start

2022-05-28T13:37:09Z

Stubby, but a start

New page

The '''KA750 CPU''' was the [[Central Processing Unit|CPU]] of the [[VAX-11/750]].

{{stub}}

==External links==

* [http://www.bitsavers.org/pdf/dec/vax/750/EK-KA750-TD-002_VAX_750_CPU_Technical_Description_198103.pdf VAX-11/750 Central Processing Unit Technical Description]
* [http://www.bitsavers.org/pdf/dec/vax/750/Introduction_to_the_COMET_Microarchitecture_198003.pdf Introduction to the COMET Microarchitecture]
* [http://www.bitsavers.org/pdf/dec/vax/750/MP01024_KA750_Engineering_Drawings_198009.pdf KA750 Field Maintenance Print Set] (MP01024)

[[Category: DEC VAX Processors]]

@@ Line 41: / Line 41: @@
 * [http://www.bitsavers.org/pdf/dec/vax/750/Introduction_to_the_COMET_Microarchitecture_198003.pdf Introduction to the COMET Microarchitecture]
 * [http://www.bitsavers.org/pdf/dec/vax/750/MP01024_KA750_Engineering_Drawings_198009.pdf KA750 Field Maintenance Print Set] (MP01024)
 * [https://web.archive.org/web/20071004184501/http://computer-refuge.org/compcollect/dec/vax/11750/L0002-big.jpg L0002 (DPM)] - Data Path Module image
 * [https://web.archive.org/web/20071004184310/http://computer-refuge.org/compcollect/dec/vax/11750/L0003-big.jpg L0003 (MIC)] - Memory Interconnect image

@@ Line 1: / Line 1: @@
 [[Image:VAX750block.jpg|right|thumb|300px|VAX-11/750 system block diagram, showing the major KA750 functional units]]
-The '''KA750 CPU''' was the [[Central Processing Unit|CPU]] of the [[VAX-11/750]].It was a [[synchronous]] [[microcode]]d design. Internally, there were several main [[bus]]ses connecting together functional units within the CPU:
+The '''KA750 CPU''' was the [[Central Processing Unit|CPU]] of the [[VAX-11/750]]. It was a [[synchronous]] [[microcode]]d design. Internally, there were several main [[bus]]ses connecting together functional units within the CPU:
 * MBus
@@ Line 21: / Line 21: @@
 * L0005 CPU Control Store (CCS) - microcode [[read-only memory|ROMs]], interface to optional KU750 Writable Control Store (WCS - sometimes informally called the User Control Store - on a [[daughter-board]] of the CCS)
-The L0005 CCS was later replaced by the L0008 Patchable Control Store (PCS). Originally, the concept was that the KA750's microcode would not change often, so it was stored in [[read-only memory|PROM (unlike the [[KL10]] and [[KA780 CPU|KA780]]). This turned out to be incorrect; like most software, bugs were found regularly. The PCS is designed to store the basic microcode in PROM, but to allow it to be 'patched' dynamically.
+The L0005 CCS was later replaced by the L0008 Patchable Control Store (PCS). Originally, the concept was that the KA750's microcode would not change often, so it was stored in [[read-only memory|PROM]] (unlike the [[KL10]] and [[KA780 CPU|KA780]]). This turned out to be incorrect; like most software, bugs were found regularly. The PCS was designed to store the basic microcode in PROM, but to allow it to be 'patched' dynamically.
-CPU options use other boards:
+CPU options used other boards:
 * L0006 - KC750 Remote Diagnostic Module (RDM)
@@ Line 32: / Line 32: @@
 ==Backplane details==
-As mentioned in the main /750 article, the CPU slots in the backplane are all customized to particular cards by the buses which run to that slot. The MBus and WBus both run to the DPM, MIC and FPA cards/slots; the UBI card/slot has only the WBus, but not the MBus. The [[CPU/Memory Interconnect bus|CMI]] runs to some cards/slots - MIC and UBI - but not others: not the DPM, nor the FPA.
+As mentioned in the main /750 article, the CPU slots in the backplane are all customized to particular cards by the buses which run to that slot. The MBus and WBus both run to the DPM, MIC and FPA cards/slots; the UBI card/slot has only the WBus, but not the MBus. The [[CPU/Memory Interconnect|CMI]] runs to some cards/slots - MIC and UBI - but not others: not the DPM, nor the FPA.
 {{semi-stub}}

@@ Line 25: / Line 25: @@
 CPU options use other boards:
-* L0006 - Remote Diagnostic Module (RDM)
+* L0006 - KC750 Remote Diagnostic Module (RDM)
 * L0001 - FP750 Floating-Point Accelerator (FPA)

← Older revision		Revision as of 21:28, 3 June 2022
Line 29:		Line 29:

	The base CPU does support [[floating point]], but implemented entirely in microcode; the FP750 increases floating-point performance substantially.		The base CPU does support [[floating point]], but implemented entirely in microcode; the FP750 increases floating-point performance substantially.
		+
		+	==Backplane details==
		+
		+	As mentioned in the main /750 article, the CPU slots in the backplane are all customized to particular cards by the buses which run to that slot. The MBus and WBus both run to the DPM, MIC and FPA cards/slots; the UBI card/slot has only the WBus, but not the MBus. The [[CPU/Memory Interconnect bus\|CMI]] runs to some cards/slots - MIC and UBI - but not others: not the DPM, nor the FPA.

	{{semi-stub}}		{{semi-stub}}

@@ Line 1: / Line 1: @@
 [[Image:VAX750block.jpg|right|thumb|300px|VAX-11/750 system block diagram, showing the major KA750 functional units]]
-The '''KA750 CPU''' was the [[Central Processing Unit|CPU]] of the [[VAX-11/750]].It was a [[synchronous]] [[microcode]]d design. It was primarily implemented in [[gate array]] [[integrated circuit|chips]] holding 400 NAND [[gate]]s; they were configured at manufacture time into the 39 different types used in the /750.
+The '''KA750 CPU''' was the [[Central Processing Unit|CPU]] of the [[VAX-11/750]].It was a [[synchronous]] [[microcode]]d design. Internally, there were several main [[bus]]ses connecting together functional units within the CPU:
 * MBus
@@ Line 10: / Line 8: @@
 * RBus
-The MBus and WBus are [[tri-state]], 32 bits wide; fields in the micro-[[instruction]]s specify the source using each bus on each cycle. The RBus connects scratchpad [[register]]s to the [[arithmetic logic unit|ALU]] and 'super rotator'.
+The MBus and WBus are [[tri-state]], 32 bits wide; fields in the micro-[[instruction]]s specify the source which will use each bus on each cycle. The RBus connects scratchpad [[register]]s to the [[arithmetic logic unit|ALU]] and 'super rotator'.
 Microcode supported micro-[[subroutine]]s, up to 15 levels deep.
@@ Line 21: / Line 19: @@
 * L0003 Memory Interconnect (MIC) - [[virtual memory]] translation buffer, [[cache]], [[main memory]] interface
 * L0004 [[UNIBUS]] Interface (UBI) - UNIBUS control and function, ancillary functions
-* L0005 CPU Control Store (CCS) - microcode [[read-only memory|ROMs]], interface to optional writable control store (WCS)
+* L0005 CPU Control Store (CCS) - microcode [[read-only memory|ROMs]], interface to optional KU750 Writable Control Store (WCS - sometimes informally called the User Control Store - on a [[daughter-board]] of the CCS)
-Options use other boards:
+The L0005 CCS was later replaced by the L0008 Patchable Control Store (PCS). Originally, the concept was that the KA750's microcode would not change often, so it was stored in [[read-only memory|PROM (unlike the [[KL10]] and [[KA780 CPU|KA780]]). This turned out to be incorrect; like most software, bugs were found regularly. The PCS is designed to store the basic microcode in PROM, but to allow it to be 'patched' dynamically.
 * L0006 - Remote Diagnostic Module (RDM)
-* L0001 - Floating-Point Accelerator (FPA)
+* L0001 - FP750 Floating-Point Accelerator (FPA)
 {{semi-stub}}

← Older revision		Revision as of 13:39, 3 June 2022
Line 1:		Line 1:
		+	[[Image:VAX750block.jpg\|right\|thumb\|300px\|VAX-11/750 system block diagram, showing the major KA750 functional units]]
		+
	The '''KA750 CPU''' was the [[Central Processing Unit\|CPU]] of the [[VAX-11/750]].It was a [[synchronous]] [[microcode]]d design. It was primarily implemented in [[gate array]] [[integrated circuit\|chips]] holding 400 NAND [[gate]]s; they were configured at manufacture time into the 39 different types used in the /750.		The '''KA750 CPU''' was the [[Central Processing Unit\|CPU]] of the [[VAX-11/750]].It was a [[synchronous]] [[microcode]]d design. It was primarily implemented in [[gate array]] [[integrated circuit\|chips]] holding 400 NAND [[gate]]s; they were configured at manufacture time into the 39 different types used in the /750.