KB11-A CPU - Revision history

Jnc: rm bloat

2023-07-02T19:08:08Z

rm bloat

Larsbrinkhoff: Narrow down category.

2022-10-11T10:31:36Z

Narrow down category.

Jnc: /* External links */ correct title

2022-03-06T17:31:52Z

‎External links: correct title

Jnc: /* External links */ +man, eng drws

2022-03-06T16:32:58Z

‎External links: +man, eng drws

Jnc: /* Parity */ regs in MS11

2019-02-05T16:14:20Z

‎Parity: regs in MS11

Jnc: add early parity stuff

2019-01-22T19:46:09Z

add early parity stuff

Jnc: Refer to MS11 for new page on it

2018-05-20T11:18:36Z

Refer to MS11 for new page on it

Jnc: fix cats

2018-05-14T00:11:54Z

fix cats

Jnc: /* See also */ Oops!

2018-05-06T15:01:55Z

‎See also: Oops!

Jnc: See also

2018-05-06T15:01:16Z

← Older revision		Revision as of 19:08, 2 July 2023
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	* [[KB11-D CPU]]		* [[KB11-D CPU]]

−	~~{{PDP-11}}~~	+	[[Category: PDP-11 UNIBUS Processors]]
−
−	[[Category:PDP-11 UNIBUS Processors]]

← Older revision		Revision as of 10:31, 11 October 2022
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	{{PDP-11}}		{{PDP-11}}

−	[[Category:PDP-11 ~~Processors]]~~	+	[[Category:PDP-11 UNIBUS Processors]]
−	~~[[Category:~~UNIBUS Processors]]

@@ Line 40: / Line 40: @@
 * [http://www.bitsavers.org/pdf/dec/pdp11/1145/KB11-A_Maint.pdf KB11-A central processor unit maintenance manual] (DEC-11-HKBB-D)
-* [http://www.bitsavers.org/pdf/dec/pdp11/1145/EK-KB11A-MM-004_Aug76.pdf KB11-A Central Processor Unit Maintenance Manual] (EK-KB11A-MM-004)
+* [http://www.bitsavers.org/pdf/dec/pdp11/1145/EK-KB11A-MM-004_Aug76.pdf KB11-A,D central processor unit maintenance manual] (EK-KB11A-MM-004)
 * [http://www.bitsavers.org/pdf/dec/pdp11/1145/KB11-A_revS_Engineering_Drawings_Dec1973.pdf KB11-A central processor unit engineering drawings] (KB11A-19-S)
 * [http://www.bitsavers.org/pdf/dec/pdp11/1145/KB11-A_Central_Processor_Unit_Engineering_Drawings_Apr76.pdf KB11-A central processor unit engineering drawings] (KB11A-65-AA)

@@ Line 31: / Line 31: @@
 ==Parity==
-In the ''pdp-11/45 processsor handbook'' (1972 and 1973 editions) a little-known "Appendix E: Memory Parity", referred to in "2.5.6 Memory Parity", indicates that there are "16 memory status registers ... each one associated with an 8K section of memory". One bit in each register is 'Halt Enable': "[when] set, the machine will execute a [[halt]] if a parity error occurs". (When clear, the machine will [[trap]] to 4!)
+In the ''pdp-11/45 processor handbook'' (1972 and 1973 editions) a little-known "Appendix E: Memory Parity", referred to in "2.5.6 Memory Parity", indicates that there are "16 memory status registers ... each one associated with an 8K section of memory". One bit in each register is 'Halt Enable': "[when] set, the machine will execute a [[halt]] if a parity error occurs". (When clear, the machine will [[trap]] to 4!)
 These registers, despite the impression given here, are not actually in the KB11-A, but rather in the MS11.
@@ Line 37: / Line 37: @@
 A very early version of the KB11-A, which actually made it into the field, does halt the CPU on a parity error on the UNIBUS. This was later changed to the canonical trap to 0114.
-== Documentation ==
+==External links==
-* [http://toresbe.dreamhosters.com/redirect.php?res=bitsavers&doc=dec/pdp11/1145/EK-KB11A-MM-004_Aug76.pdf EK-KB11A-MM-xxx KB11-A Central Processor Unit Maintenance Manual]
+* [http://www.bitsavers.org/pdf/dec/pdp11/1145/KB11-A_Maint.pdf KB11-A central processor unit maintenance manual] (DEC-11-HKBB-D)
 ==See also==

@@ Line 31: / Line 31: @@
 ==Parity==
-An apparent 'tombstone' from an early specification of the KB11-A can be found in the ''pdp-11/45 processsor handbook'' (1972 and 1973 editions) where a little-known "Appendix E: Memory Parity", referred to in "2.5.6 Memory Parity", indicates that there are "16 memory status registers ... each one associated with an 8K section of memory". One bit in each register is 'Halt Enable': "[when] set, the machine will execute a [[halt]] if a parity error occurs". (When clear, the machine will [[trap]] to 4!) They also provided [[UNIBUS parity#Second_version|detailed parity control]].
+In the ''pdp-11/45 processsor handbook'' (1972 and 1973 editions) a little-known "Appendix E: Memory Parity", referred to in "2.5.6 Memory Parity", indicates that there are "16 memory status registers ... each one associated with an 8K section of memory". One bit in each register is 'Halt Enable': "[when] set, the machine will execute a [[halt]] if a parity error occurs". (When clear, the machine will [[trap]] to 4!)
-It is not known whether these registers were actually implemented in an early version of the KB11-A, and if so, exactly what functionality was included. A slightly later very early version, which actually made it into the field, does not have these registers, but does halt the CPU on a parity error.
+These registers, despite the impression given here, are not actually in the KB11-A, but rather in the MS11.
 == Documentation ==

← Older revision		Revision as of 19:46, 22 January 2019
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	which comprise the KT11-C.		which comprise the KT11-C.
		+
		+	==Parity==
		+
		+	An apparent 'tombstone' from an early specification of the KB11-A can be found in the ''pdp-11/45 processsor handbook'' (1972 and 1973 editions) where a little-known "Appendix E: Memory Parity", referred to in "2.5.6 Memory Parity", indicates that there are "16 memory status registers ... each one associated with an 8K section of memory". One bit in each register is 'Halt Enable': "[when] set, the machine will execute a [[halt]] if a parity error occurs". (When clear, the machine will [[trap]] to 4!) They also provided [[UNIBUS parity#Second_version\|detailed parity control]].
		+
		+	It is not known whether these registers were actually implemented in an early version of the KB11-A, and if so, exactly what functionality was included. A slightly later very early version, which actually made it into the field, does not have these registers, but does halt the CPU on a parity error.

	== Documentation ==		== Documentation ==

@@ Line 1: / Line 1: @@
 The '''KB11-A''' [[Central Processing Unit|CPU]] is the earlier CPU for the [[PDP-11/45]]. The optional [[FP11-B Floating-Point Processor]] and [[KT11-C Memory Management Unit]] of the PDP-11/45 plugged into the CPU's [[backplane]].
-In addition to [[main memory]] on the [[UNIBUS]], the KB11-A could also use high-speed [[Metal Oxide Semiconductor|MOS]] or [[bipolar]] memory, specific to the PDP-11/45, which plugged into a special [[bus]], the Fastbus, which was also part of the CPU's backplane.
+In addition to [[main memory]] on the [[UNIBUS]], the KB11-A could also use the special high-speed [[MS11 Semiconductor Memory System]], specific to the PDP-11/45, which plugged into a special [[bus]], the Fastbus, which was also part of the CPU's backplane.
 The KB11-A was the first of a [[KB11|series of PDP-11 CPUs]] which were modified versions of this design.

← Older revision		Revision as of 00:11, 14 May 2018
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	{{PDP-11}}		{{PDP-11}}

−	[[Category: ~~UNIBUS~~ PDP-~~11s~~]]	+	[[Category:PDP-11 Processors]]
		+	[[Category:UNIBUS Processors]]

@@ Line 35: / Line 35: @@
 ==See also==
-* [[KB11-B CPU]]
+* [[KB11-D CPU]]
 {{PDP-11}}
 [[Category: UNIBUS PDP-11s]]