KB11-B CPU - Revision history

Jnc: rm bloat

2023-07-02T19:08:49Z

rm bloat

Jnc: board re-use

2022-10-15T13:27:53Z

board re-use

Jnc: /* External links */ +docs at Bitsavers

2022-10-13T16:19:27Z

‎External links: +docs at Bitsavers

Larsbrinkhoff: /* See also */ Narrow down category.

2022-10-11T10:31:58Z

‎See also: Narrow down category.

Jnc: Fix cats

2018-05-13T22:09:34Z

Fix cats

Jnc: Update board names, etc

2018-05-13T21:58:35Z

Update board names, etc

Jnc: Copyedit

2018-05-13T00:43:01Z

Copyedit

Jnc: A start

2018-05-13T00:12:07Z

A start

New page

The '''KB11-B''' [[Central Processing Unit|CPU]] is the earlier CPU for the [[PDP-11/70]]. The optional [[FP11-B Floating-Point Processor]] (full [[FP11 floating point]]), and up to four [[RH70 MASSBUS controller]] plugged into the CPU's [[backplane]].

The KB11-B used a special memory bus, unique to the -11/70, for its [[bus]] to [[main memory]]; this bus allowed it to have up to 4 mega-[[byte]]s of main memory. All devices were attached to a separate [[UNIBUS]]; [[Direct Memory Access|DMA]] devices could gain access to the memory via a [[UNIBUS map]] which connected the two, and also mapped UNIBUS addresses to main memory addresses. High-speed devices could be attached to [[MASSBUS]] [[controller]]s.

Full [[PDP-11 Memory Management]] and a [[cache]] were standard on all KB11-B's.

==Boards==

The basic KB11-B consisted of fifteen [[DEC card form factor|hex]] boards:

* M8130 Data Paths
* M8131 General Registers and ALU Control
* M8132 Instruction Register Decode and Condition Codes
* M8133 ROM and ROM Control
* M8134 Processor Data and UNIBUS Registers
* M8135 Trap and Miscellaneous Control
* M8136 UNIBUS and Console Control
* M8137 System Address Paths
* M8138 System Status Registers
* M8140 System Descriptor/Console Control
* M8141 UNIBUS Map
* M8142 Cache Control
* M8143 Address Memory
* M8144 Data Memory
* M8145 Cache Data Paths

and a quad board:

* M8139 Timing Generator

The M8130 through M8139 boards are based on those of the [[KB11-A CPU]] of the [[PDP-11/45]], upon which the KB11-B is based; the rest implement the -11/70's extensions (cache - M8142-45, UNIBUS Map - M8141, etc).

==See also==

* [[KB11-C CPU]]

{{PDP-11}}

[[Category: UNIBUS PDP-11s]]

@@ Line 46: / Line 46: @@
 * [http://bitsavers.org/pdf/dec/pdp11/1170/1170_Engineering_Drawings_revB_1977.pdf KB11-B 16-Bit Processor Engineering Drawings (5/1977)]
 * [https://forum.vcfed.org/index.php?threads/pdp-11-45-part-5.54005/post-656568 PDP 11/45, Part 5]
 [[Category: PDP-11 UNIBUS Processors]]

@@ Line 30: / Line 30: @@
 * M8139 Timing Generator
 The M8130 through M8139 boards are based on those of the KB11-A CPU of the -11/45; the rest implement the -11/70's extensions (cache - M8142-45, UNIBUS Map - M8141, etc).
 ==See also==
@@ Line 41: / Line 45: @@
 * [http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/EK-KB11B-TM-001%20KB11-B%20Processor%20Manual%20(PDP-1170).pdf KB11-B Processor Manual (PDP-11/70)] (EK-KB11B-TM-001)
 * [http://bitsavers.org/pdf/dec/pdp11/1170/1170_Engineering_Drawings_revB_1977.pdf KB11-B 16-Bit Processor Engineering Drawings (5/1977)]
 {{PDP-11}}
 [[Category: PDP-11 UNIBUS Processors]]

← Older revision		Revision as of 10:31, 11 October 2022
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	{{PDP-11}}		{{PDP-11}}

−	[[Category: PDP-11 ~~Processors]]~~	+	[[Category: PDP-11 UNIBUS Processors]]
−	~~[[Category:~~ UNIBUS Processors]]

← Older revision		Revision as of 22:09, 13 May 2018
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	{{PDP-11}}		{{PDP-11}}

−	[[Category: ~~UNIBUS~~ PDP-~~11s~~]]	+	[[Category: PDP-11 Processors]]
		+	[[Category: UNIBUS Processors]]

@@ Line 1: / Line 1: @@
 The '''KB11-B''' [[Central Processing Unit|CPU]] is the earlier CPU for the [[PDP-11/70]]. It is heavily based on the [[PDP-11/45]]'s [[KB11-A CPU]]; the -11/70 is basically an -11/45 with a [[cache]], more [[main memory]], and provision for high/speed [[input/output|I/O]] [[device controller]]s for [[MASSBUS]] devices.
-Full [[PDP-11 Memory Management]] and the cache were standard on all KB11-B's. It used a special 32-[[bit]] wide memory [[bus]], the Main Memory Bus, unique to the -11/70, for its bus to main memory; this bus allowed it to have up to 4 mega-[[byte]]s of main memory.
+Full [[PDP-11 Memory Management]] and the cache were standard on all KB11-B's. It used a special 32-[[bit]] wide memory [[bus]], the Main Memory Bus, unique to the -11/70, for its bus to main memory; in addition to the speedup of doubling the width, this bus also allowed it to have up to 4 mega-[[byte]]s of main memory.
 All devices were attached to a separate [[UNIBUS]]; [[Direct Memory Access|DMA]] devices could gain access to the memory via a [[UNIBUS map]] which connected the two, and also mapped UNIBUS addresses to main memory addresses. High-speed devices could be attached to MASSBUS controllers.
@@ Line 20: / Line 20: @@
 * M8137 System Address Paths
 * M8138 System Status Registers
-* M8140 System Descriptor/Console Control
+* M8140 System Descriptor amd Console Cables
 * M8141 UNIBUS Map
 * M8142 Cache Control
-* M8143 Address Memory
+* M8143 Cache Address Memory
-* M8144 Data Memory
+* M8144 Cache Data Memory
 * M8145 Cache Data Paths