KD11-E/EA microcode - Revision history

Jnc: /* Microcode */ Make note tags anchors, so they can be linked to

2025-07-24T14:58:00Z

‎Microcode: Make note tags anchors, so they can be linked to

Jnc: /* Microcode */ typo

2025-07-24T12:43:44Z

‎Microcode: typo

Jnc: /* External links */ - Move ext link to FMPS to External links section; annotate as to page numbers

2024-10-04T17:26:26Z

‎External links: - Move ext link to FMPS to External links section; annotate as to page numbers

ForOldHack: /* Added Enginering drawings for The KD-11-EA */

2024-10-03T22:47:38Z

‎Added Enginering drawings for The KD-11-EA

Jnc: /* Microcode */ typo

2022-11-05T03:02:20Z

‎Microcode: typo

Jnc: Better cat

2022-10-12T00:32:47Z

Better cat

Jnc: /* Microcode */ clarify source of BUT bits

2019-01-18T01:59:37Z

‎Microcode: clarify source of BUT bits

Jnc: /* Microcode */ Add instruction decode targets

2019-01-15T20:05:43Z

‎Microcode: Add instruction decode targets

Jnc: /* Microcode */ clarifications

2019-01-15T09:47:19Z

‎Microcode: clarifications

Jnc: /* Microcode */ Add next uninst column to table

2019-01-14T21:33:51Z

‎Microcode: Add next uninst column to table

Show changes

@@ Line 582: / Line 582: @@
 | colspan = "4" | &nbsp;
 |-
-| 340<sup>1</sup> || 10-Q || 341 || Output RSRC to stack
+| 340<span id="Note1"><sup>1</sup></span> || 10-Q || 341 || Output RSRC to stack
 |-
 | 341 || 10-R || 342 || Move PC to RSRC
@@ Line 614: / Line 614: @@
 | 356 || 12-B || 050 || Shift operand
 |-
-| 357<sup>2</sup> || 12-F || 370 || Increment RDST
+| 357<span id="Note2"><sup>2</sup></span> || 12-F || 370 || Increment RDST
 |-
 | colspan = "4" | &nbsp;
@@ Line 744: / Line 744: @@
 | colspan = "4" | &nbsp;
 |-
-| 450<sup>3</sup> || 17-II || 744 || Step SP
+| 450<span id="Note3"><sup>3</sup></span> || 17-II || 744 || Step SP
 |-
 | 451 || 22-K || 471 || Add divisor to remainder
@@ Line 1,026: / Line 1,026: @@
 | 645 || 17-FF || 535 || Data to PC
 |-
-| 646<sup>4</sup> || 26-L || 320 || Fetch new PC
+| 646<span id="Note4"><sup>4</sup></span> || 26-L || 320 || Fetch new PC
 |-
 | 647 || 26-CC || 654 || Add 2 to R15
@@ Line 1,231: / Line 1,231: @@
 Notes:
-- prints say 346; '6' written for '0'
+[[#Note1|1]] - prints say 346; '6' written for '0'
 <br>
-- prints say 375; digit swap
+[[#Note2|2]] - prints say 375; digit swap
 <br>
-- prints say 540; digit swap
+[[#Note3|3]] - prints say 540; digit swap
 <br>
-- prints give a different 'next' from a microcode dump
+[[#Note4|4]] - prints give a different 'next' from a microcode dump
 + - This is the main instruction decode multi-way branch. Possible next microinstructions include:

@@ Line 732: / Line 732: @@
 | 442 || 21-G || 640,650,660,670 || Shift remainder left, test sign of divisor, test LSB of quotient
 |-
-| 443 || 22-N || 615 || Srore remainder
+| 443 || 22-N || 615 || Store remainder
 |-
-| 444 || 22-D || 614 || Srore remainder
+| 444 || 22-D || 614 || Store remainder
 |-
 | 445 || 24-E || 635 || Save BX in B, clear N bit
@@ Line 876: / Line 876: @@
 | 542 || 17-Y || 000 || Mask and set condition codes
 |-
-| 543 || 22-M || 614 || Srore remainder
+| 543 || 22-M || 614 || Store remainder
 |-
-| 544 || 22-E || 615 || Srore remainder
+| 544 || 22-E || 615 || Store remainder
 |-
 | 545 || 24-F || 635 || Save BX in B, set N bit

@@ Line 2: / Line 2: @@
 The difference is that the [[microinstruction]] 17-JJ is stored in location 002 in the KD11-E, and location 0744 in the KD11-EA. The reason for the change is unknown. Also, a dump of the KD11-EA microcode gives a different 'next microinstuction', from that given in the prints, for microinstruction 26-L (location 646); the prints show 9-F (location 320) as the next, but the dump gives 745. Again, the reason is unknown.
 ==Flow chart index==
@@ Line 1,250: / Line 1,248: @@
 ==External links==
 * [http://www.bitsavers.org/pdf/dec/pdp11/1134/m8266_ucode.out.txt Dump of KD11-EA microcode on BitSavers] (in symbolic form)
 [[Category: PDP-11 UNIBUS Processors]]

← Older revision		Revision as of 22:47, 3 October 2024
Line 2:		Line 2:

	The difference is that the [[microinstruction]] 17-JJ is stored in location 002 in the KD11-E, and location 0744 in the KD11-EA. The reason for the change is unknown. Also, a dump of the KD11-EA microcode gives a different 'next microinstuction', from that given in the prints, for microinstruction 26-L (location 646); the prints show 9-F (location 320) as the next, but the dump gives 745. Again, the reason is unknown.		The difference is that the [[microinstruction]] 17-JJ is stored in location 002 in the KD11-E, and location 0744 in the KD11-EA. The reason for the change is unknown. Also, a dump of the KD11-EA microcode gives a different 'next microinstuction', from that given in the prints, for microinstruction 26-L (location 646); the prints show 9-F (location 320) as the next, but the dump gives 745. Again, the reason is unknown.
		+
		+	[https://bitsavers.org/pdf/dec/pdp11/1134/MP00190_1134A_KD11-EA.pdf Engineering drawings for the KD11-EA CPU]

	==Flow chart index==		==Flow chart index==

@@ Line 132: / Line 132: @@
 | colspan = "4" | &nbsp;
 |-
-| 030 || 11-A || 343 || Swap destination operatand to R12
+| 030 || 11-A || 343 || Swap destination operand to R12
 |-
 | 031 || 11-C || 355 || Fetch swapped destination operand

← Older revision		Revision as of 00:32, 12 October 2022
Line 1,250:		Line 1,250:
	* [http://www.bitsavers.org/pdf/dec/pdp11/1134/m8266_ucode.out.txt Dump of KD11-EA microcode on BitSavers] (in symbolic form)		* [http://www.bitsavers.org/pdf/dec/pdp11/1134/m8266_ucode.out.txt Dump of KD11-EA microcode on BitSavers] (in symbolic form)

−	[[Category: PDP-11 Processors]]	+	[[Category: PDP-11 UNIBUS Processors]]

@@ Line 65: / Line 65: @@
 The following table, indexed by microinstruction number (in octal), gives the location of each microinstruction in the flow diagrams, the next microinstruction(s), and the operation performed by that microinstruction.
-The microengine of the KD11-E/EA uses a technique called a 'branch microtest' (abbreviated to 'BUT' in the drawings), where the 'next microinstruction' field (in each microinstruction - there is no 'micro-PC') can be OR'd with various bits, to provide [[conditional branch]]ing. More than one bit at a time can be OR'd, thereby providing multi-way branching.
+The microengine of the KD11-E/EA uses a technique called a 'branch microtest' (abbreviated to 'BUT' in the drawings), where the 'next microinstruction' field (in each microinstruction - there is no 'micro-PC') can be OR'd with various bits provided by the [[logic]] in the KD11-E/EA, to provide [[conditional branch]]ing. More than one bit at a time can be OR'd, thereby providing multi-way branching.
-In the table below, for every microinstruction which can have variation as to the next microinstruction, all possible 'next microinstruction' destinations are listed. Note that depending on the bit(s) being tested, various bits of the 'next microinstruction' [[address]] may be set. This can result in rather odd code layout, since a multi-way branch may require microinstructions to be scattered throughout the [[address space]], with a fixed numerical relationship among their addresses - the exact relationship depending on which bit is being tested.
+In the table below, for every microinstruction which can have variation as to the next microinstruction, all possible 'next microinstruction' destinations are listed. Note that depending on the bit(s) being tested, various bits of the 'next microinstruction' [[address]] may be set.
 One microinstruction (015), the main dispatch in instruction decoding, greatly extends the technique, with the aid of an instruction decode [[read-only memory|ROM]], so the next microinstruction in its case may be one of dozens. They are mostly arranged in groups of eight, with one of each group for each [[PDP-11 architecture#Addressing modes|addressing mode]] in the [[operand]]s. (In the table below, such a destination is notated as 'YYx'.)

@@ Line 238: / Line 238: @@
 | colspan = "4" | &nbsp;
 |-
-| 110 || 3-A || 05x, 07x. 06x || Source operand to R12 and BREG
+| 110 || 3-A || 05x, 06x. 07x || Source operand to R12 and BREG
 |-
-| 111 || 3-B || 05x, 07x. 06x || Fetch source operand
+| 111 || 3-B || 05x, 06x. 07x || Fetch source operand
 |-
 | 112 || 3-D || 205 || Fetch source operand
@@ Line 1,236: / Line 1,236: @@
 <br>
 - prints give a different 'next' from a microcode dump
 ==External links==

@@ Line 67: / Line 67: @@
 The microengine of the KD11-E/EA uses a technique called a 'branch microtest' (abbreviated to 'BUT' in the drawings), where the 'next microinstruction' field (in each microinstruction - there is no 'micro-PC') can be OR'd with various bits, to provide [[conditional branch]]ing. More than one bit at a time can be OR'd, thereby providing multi-way branching.
-In the table below, for every microinstruction which can have variation as to the next microinstruction, all possible 'next microinstruction' destinations are listed. Note that depending on the bit(s) being tested, various bits of the 'next microinstruction' [[address]] may be set. This can result in rather odd code layout, since a multi-way brach may require microinstructions to be scattered, with a fixed numerical relationship among the addresses - the exact relationship depending on which bit is being tested.
+In the table below, for every microinstruction which can have variation as to the next microinstruction, all possible 'next microinstruction' destinations are listed. Note that depending on the bit(s) being tested, various bits of the 'next microinstruction' [[address]] may be set. This can result in rather odd code layout, since a multi-way branch may require microinstructions to be scattered throughout the [[address space]], with a fixed numerical relationship among their addresses - the exact relationship depending on which bit is being tested.
-One microinstruction (015), the main dispatch in instruction decoding, greatly extends the technique (with the aid of an instruction decode [[read-only memory|ROM]]), so the next microinstruction in its case may be one of dozens. They are mostly arranged in groups of eight, one for each [[PDP-11 architecture#Addressing modes|addressing mode]] in the [[operand]]s. (In the table below, such a destination is notated as 'YYx'.)
+One microinstruction (015), the main dispatch in instruction decoding, greatly extends the technique, with the aid of an instruction decode [[read-only memory|ROM]], so the next microinstruction in its case may be one of dozens. They are mostly arranged in groups of eight, with one of each group for each [[PDP-11 architecture#Addressing modes|addressing mode]] in the [[operand]]s. (In the table below, such a destination is notated as 'YYx'.)
 During the transcription of this information, a number of errors in the drawings were found - places were two different microinstructions were assigned to the same location. These have been corrected (and checked against a dump of the microcode).