KD11-K CPU - Revision history

Larsbrinkhoff: /* External links */ Narrow down category.

2022-10-11T10:34:04Z

‎External links: Narrow down category.

Jnc: /* Implementation */ UNIBUS designations

2022-01-12T00:46:25Z

‎Implementation: UNIBUS designations

Jnc: typo

2022-01-11T21:52:01Z

typo

Jnc: two UNIBUS connectors

2022-01-11T21:51:07Z

two UNIBUS connectors

Jnc: /* External links */ +FMPS, manuals - also backplane layout

2022-01-11T14:19:12Z

‎External links: +FMPS, manuals - also backplane layout

Jnc: add link for clue as to jargon meaning

2019-03-04T15:55:15Z

add link for clue as to jargon meaning

Jnc: /* Microcode */ start list at 0

2019-03-04T01:39:39Z

‎Microcode: start list at 0

Jnc: Add ucodr addr space alloc

2019-03-04T01:34:22Z

Add ucodr addr space alloc

Jnc: An OK start

2019-03-02T15:58:52Z

An OK start

New page

The '''KD11-K''' was the [[Central Processing Unit|CPU]] of the [[PDP-11/60]]. It was a [[microcode]]d CPU, using 48-bit wide micro-words; it provided the [[PDP-11 Memory Management|subset PDP-11 memory management]], and used the [[UNIBUS]] for [[main memory]] access (although a built-in [[cache]] was standard).

It consisted of a custom 14-slot [[backplane]], and 6 [[DEC card form factor|hex]] [[printed circuit board|boards]]:

* uWord (M7872)
* Decode (M7873)
* Data Path (M7874)
* KT/Cache (M7875)
* Timing (M7876)
* Status (M7827)

for the basic CPU, held in slots 2-7 of the backplane.

It provided the full [[FP11 floating point]] using microcode; as an option, the [[FP11-E Floating Point Processor]], a 4 hex board [[co-processor]] which provided a high-performance implementation, was also available; it used slots 8-11 of the backplane.

A single slot in the backplane, slot 1, is available to hold either a User Control Store (1KW of read-write microcode), an Extended Control Store ([[ROM]] microcode), or a Diagnostic Control Store.

The remaining slots, 12-14, were [[Small Peripheral Controller|SPC]] slots.

{{PDP-11}}

[[Category: PDP-11 Processors]]
[[Category: UNIBUS Processors]]

← Older revision		Revision as of 10:34, 11 October 2022
Line 79:		Line 79:
	** [http://www.bitsavers.org/pdf/dec/pdp11/1160/MP00500_1160WCS_Nov77.pdf KU116-AA Field Maintenance Print Set] (MP00500)		** [http://www.bitsavers.org/pdf/dec/pdp11/1160/MP00500_1160WCS_Nov77.pdf KU116-AA Field Maintenance Print Set] (MP00500)

−	[[Category: PDP-11 ~~Processors]]~~	+	[[Category: PDP-11 UNIBUS Processors]]
−	~~[[Category:~~ UNIBUS Processors]]

@@ Line 62: / Line 62: @@
 | 12 || colspan="2" style="text-align:center;" | Unused || colspan="4" style="text-align:center;" | SPC
 |-
-| 13 || colspan="2" style="text-align:center;" | Bootstrap || colspan="4" style="text-align:center;" | SPC
+| 13 || colspan="2" style="text-align:center;" | Memory UNIBUS/Bootstrap || colspan="4" style="text-align:center;" | SPC
 |-
-| 14 || colspan="2" style="text-align:center;" | UNIBUS Out || colspan="4" style="text-align:center;" | SPC
+| 14 || colspan="2" style="text-align:center;" | I/O UNIBUS/Terminator || colspan="4" style="text-align:center;" | SPC
 |}

@@ Line 3: / Line 3: @@
 It provided the full [[FP11 floating point]] using [[microcode]]; as an option, the [[FP11-E Floating Point Processor]], a 4 hex board [[co-processor]] which provided a high-performance implementation, was also available. Also available were either a User Control Store (1KW of read-write microcode), an Extended Control Store ([[ROM]] microcode), or a Diagnostic Control Store.
-One unusual aspect was that the CPU's [[backplane]] had a separate UNIBUS connectors for [[input/output|I/O]] activity, and for memory access. The FMPS indicates (pg. 4) that devices that do [[interupt]]s and [[Direct Memory Access|DMA]] must be connected to the I/O UNIBUS, and not to the memory UNIBUS; but it also indicates (pg. 3) that there is only a single UNIBUS. (Perhaps all the [[bus grant line]]s from the bus arbitration circuitry in the CPU are only connected to the I/O connector?)
+One unusual aspect was that the CPU's [[backplane]] had a separate UNIBUS connectors for [[input/output|I/O]] activity, and for memory access. The FMPS indicates (pg. 4) that devices that do [[interrupt]]s and [[Direct Memory Access|DMA]] must be connected to the I/O UNIBUS, and not to the memory UNIBUS; but it also indicates (pg. 3) that there is only a single UNIBUS. (Perhaps all the [[bus grant line]]s from the bus arbitration circuitry in the CPU are only connected to the I/O connector?)
 ==Microcode==

@@ Line 1: / Line 1: @@
-The '''KD11-K''' was the [[Central Processing Unit|CPU]] of the [[PDP-11/60]]. It provided the [[PDP-11 Memory Management|subset PDP-11 memory management]], and used the [[UNIBUS]] for its [[main memory]] access (although a built-in [[cache]] was standard).
+The '''KD11-K''' was the [[Central Processing Unit|CPU]] of the [[PDP-11/60]]. It provided the [[PDP-11 Memory Management|subset PDP-11 memory management]], and used a [[UNIBUS]] for its [[main memory]] access (although a built-in [[cache]] was standard).
 It provided the full [[FP11 floating point]] using [[microcode]]; as an option, the [[FP11-E Floating Point Processor]], a 4 hex board [[co-processor]] which provided a high-performance implementation, was also available. Also available were either a User Control Store (1KW of read-write microcode), an Extended Control Store ([[ROM]] microcode), or a Diagnostic Control Store.
 ==Microcode==
@@ Line 20: / Line 22: @@
 ==Implementation==
-It consisted of a custom 14-slot [[backplane]], and 6 [[DEC card form factor|hex]] [[printed circuit board|boards]]:
+It consisted of a custom 14-slot backplane (([[DEC part number]] 70-12953), and 6 [[DEC card form factor|hex]] [[printed circuit board|boards]]:
 * uWord (M7872)
@@ Line 36: / Line 38: @@
 ! Slot !! A !! B !! C !! D !! E !! F
 |-
-| 1 || colspan="6" style="text-align:center;" | WCS/ECS/DCS (optional)
+| 1 || colspan="6" style="text-align:center;" | WCS or ECS or DCS (optional)
 |-
 | 2 || colspan="6" style="text-align:center;" | uWord (M7872)

@@ Line 1: / Line 1: @@
-The '''KD11-K''' was the [[Central Processing Unit|CPU]] of the [[PDP-11/60]]. It provided the [[PDP-11 Memory Management|subset PDP-11 memory management]], and used the [[UNIBUS]] for [[main memory]] access (although a built-in [[cache]] was standard).
+The '''KD11-K''' was the [[Central Processing Unit|CPU]] of the [[PDP-11/60]]. It provided the [[PDP-11 Memory Management|subset PDP-11 memory management]], and used the [[UNIBUS]] for its [[main memory]] access (although a built-in [[cache]] was standard).
-It consisted of a custom 14-slot [[backplane]], and 6 [[DEC card form factor|hex]] [[printed circuit board|boards]]:
+It provided the full [[FP11 floating point]] using [[microcode]]; as an option, the [[FP11-E Floating Point Processor]], a 4 hex board [[co-processor]] which provided a high-performance implementation, was also available. Also available were either a User Control Store (1KW of read-write microcode), an Extended Control Store ([[ROM]] microcode), or a Diagnostic Control Store.
 ==Microcode==
@@ Line 25: / Line 10: @@
 <li>Base instructions</li>
 </ol>
-# Console an Error log
+# Console and Error log
 # EIS, Initialization
 # Floating point
@@ Line 33: / Line 18: @@
 # ECS/UCS
-{{PDP-11}}
+==Implementation==
 [[Category: PDP-11 Processors]]
 [[Category: UNIBUS Processors]]

@@ Line 6: / Line 6: @@
 * Decode (M7873)
 * Data Path (M7874)
-* KT/Cache (M7875)
+* [[KT11|KT]]/Cache (M7875)
 * Timing (M7876)
 * Status (M7827)
@@ Line 12: / Line 12: @@
 for the basic CPU, held in slots 2-7 of the backplane.
-It provided the full [[FP11 floating point]] using microcode; as an option, the [[FP11-E Floating Point Processor]], a 4 hex board [[co-processor]] which provided a high-performance implementation, was also available; it used slots 8-11 of the backplane.
+It provided the full [[FP11 floating point]] using [[microcode]]; as an option, the [[FP11-E Floating Point Processor]], a 4 hex board [[co-processor]] which provided a high-performance implementation, was also available; it used slots 8-11 of the backplane.
 A single slot in the backplane, slot 1, is available to hold either a User Control Store (1KW of read-write microcode), an Extended Control Store ([[ROM]] microcode), or a Diagnostic Control Store.
@@ Line 20: / Line 20: @@
 ==Microcode==
-It was a [[microcode]]d CPU, using 48-bit wide micro-words; the [[address space]] of the micro-engine was 2<sup>12</sup> words, divided into 8 blocks. The allocation of the blocks was:
+It was a microcoded CPU, using 48-bit wide micro-words; the [[address space]] of the micro-engine was 2<sup>12</sup> words, divided into 8 blocks. The allocation of the blocks was:
 <ol start="0">