KDF11-U CPU - Revision history

Jnc: +New category

2024-02-06T14:16:23Z

+New category

← Older revision		Revision as of 14:16, 6 February 2024
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	[[Category: PDP-11 UNIBUS Processors]]		[[Category: PDP-11 UNIBUS Processors]]
			[[Category: Extended UNIBUS]]
			[[Category: DEC Documentation Errors]]

Jnc: CPU board location

2022-05-31T03:24:48Z

CPU board location

← Older revision		Revision as of 03:24, 31 May 2022
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	[[Image:KDF11-U.jpg\|300px\|thumb\|right\|KDF11-U card with [[KTF11-A memory management chip\|KTF11-A]] and [[KEF11-A floating point chip\|KEF11-A]]]]		[[Image:KDF11-U.jpg\|300px\|thumb\|right\|KDF11-U card with [[KTF11-A memory management chip\|KTF11-A]] and [[KEF11-A floating point chip\|KEF11-A]]]]

	The '''KDF11-U''' is the [[PDP-11 architecture\|PDP-11]] [[Central Processing Unit\|CPU]] for the [[PDP-11/24]]; it was implemented as a single [[DEC card form factor\|hex]] [[printed circuit board\|board]], the KDF11-UA '''M7133'''. It used the same 'Fonz' [[F-11 chip set]] as the other KDF11 CPUs; however, it used the [[UNIBUS]], unlike the [[QBUS]] of the other [[KDF11 CPUs]].		The '''KDF11-U''' is the [[PDP-11 architecture\|PDP-11]] [[Central Processing Unit\|CPU]] for the [[PDP-11/24]]; it was implemented as a single [[DEC card form factor\|hex]] [[printed circuit board\|board]], the KDF11-UA '''M7133'''. It used the same 'Fonz' [[F-11 chip set]] as the other KDF11 CPUs; however, it used the [[UNIBUS]], unlike the [[QBUS]] of the other [[KDF11 CPUs]]. It plugs into a custom slot in the likewise custom PDP-11/24 [[backplane]] ([[DEC part number]] 54-13817, assembly 70-16905).

	The board has seven 40-pin [[Dual Inline Package\|DIP]] [[chip socket]]s for the [[integrated circuit\|chipset]] (including the [[KTF11-A memory management chip\|KTF11-A]] [[PDP-11 Memory Management\|memory management]] and [[KEF11-A floating point chip\|KEF11-A]] [[floating point]] chips); it can also hold the double-width [[KEF11-B CIS chip\|KEF11-B]] 6-chip carrier implementing the [[PDP-11 Commercial Instruction Set]] (CIS) (not all KDF11 CPUs can hold this). In addition to the basic CPU functionality, the board also included two [[asynchronous serial line]]s (led out through the [[backplane]]).		The board has seven 40-pin [[Dual Inline Package\|DIP]] [[chip socket]]s for the [[integrated circuit\|chipset]] (including the [[KTF11-A memory management chip\|KTF11-A]] [[PDP-11 Memory Management\|memory management]] and [[KEF11-A floating point chip\|KEF11-A]] [[floating point]] chips); it can also hold the double-width [[KEF11-B CIS chip\|KEF11-B]] 6-chip carrier implementing the [[PDP-11 Commercial Instruction Set]] (CIS) (not all KDF11 CPUs can hold this). In addition to the basic CPU functionality, the board also included two [[asynchronous serial line]]s (led out through the [[backplane]]).

Jnc: /* See also */ +KDF11-U CPU pinout

2022-05-31T01:20:47Z

Jnc: /* ECO's */ minor copedits

2022-04-03T18:27:42Z

ECO's: minor copedits

← Older revision		Revision as of 18:27, 3 April 2022
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	E52p5 (the transceiver's input) is connected to E73p13 (an DS8640 quad NOR used as a bus reciver), in the upper left corner of K2. That produces UNIBUS PB L NOR UNIBUS PA H - i.e. a [[parity]] error has been [[UNIBUS parity\|detected in memory]] - to which the response is apparently to power-fail the system!		E52p5 (the transceiver's input) is connected to E73p13 (an DS8640 quad NOR used as a bus reciver), in the upper left corner of K2. That produces UNIBUS PB L NOR UNIBUS PA H - i.e. a [[parity]] error has been [[UNIBUS parity\|detected in memory]] - to which the response is apparently to power-fail the system!

	The incoming ACLO from the transceiver (E52p6) now has a wire going to a PTH next to E70p8. On the bottom side of the [[PCB]], there's a trace from that PTH ~~that goes~~ to E66p13 - which is the inverter (shown on K2) which converts BUF ACLO H to POWER OK H. So that answers the inevitable query about E70p1 being left floating after the etch cut: perhaps there's an etch cut somewhere that disconnected E66p13 from E70p2, so the former can now be driven by E52p6. (~~Theren~~ is a trace from that latter PTH which dives under E70, and it's hard to see it, ~~but~~ it looks like it goes to E70p2.) It would be interesting to know what they did about the E70p2 -> E66p13 connection.		The incoming ACLO from the transceiver (E52p6) now has a wire going to a PTH next to E70p8. On the bottom side of the [[printed circuit board\|PCB]], there's a trace from that PTH to E66p13 - which is the [[inverter]] (shown on K2) which converts BUF ACLO H to POWER OK H. So that answers the inevitable query about E70p1 (and its output, E70p2) being left floating after the etch cut: perhaps there's an etch cut somewhere that disconnected E66p13 from E70p2, so the former can now be driven by E52p6. (There is a trace from that latter PTH which dives under E70, and although it's hard to see it, it looks like it goes to E70p2.) It would be interesting to know what they did about the E70p2 -> E66p13 connection.

	==External links==		==External links==

Jnc: Describe un-documented ECO

2022-04-03T16:25:45Z

Describe un-documented ECO

← Older revision		Revision as of 16:25, 3 April 2022
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	===LED's===		===LED's===

	The board contains three [[Light Emitting Diode\|LED]]'s (along the upper edge), which provide [[diagnostic]] information. One (marked 'CLK') an indication that the CPU's main internal clock (on page K1 of the prints, in the very upper left corner) is running. The other two (left center, page K12) are driven by a write-only [[register]], and are used by diagnostic code in the [[bootstrap]] to indicate progress.		The board contains three [[Light Emitting Diode\|LED]]'s (along the upper edge), which provide [[diagnostic]] information. One (marked 'CLK') an indication that the CPU's main internal clock (on page K1 of the prints, in the very upper left corner) is running. The other two ('0' and '1'; left center, page K12) are driven by a write-only [[register]], and are used by diagnostic code in the [[bootstrap]] to indicate progress.

	The CLK LED is driven directly by the MCLK L internal [[signal]]; if that LED is not on, the CPU is not running. If either the bus ACLO or DCLO signals is asserted, MCLK L is off.		The CLK LED is driven directly by the MCLK L internal [[signal]]; if that LED is not on, the CPU is not running. If either the bus ACLO or DCLO signals is asserted, MCLK L is off.

			==ECO's==

			Although there's a page in the FMPS (below) which lists [[Engineering Change Order\|ECO]]'s (pg. 167 of the PDF, two pages after K14), there's at least one major ECO which doesn't seem to be listed there. It seems to be a common ECO, though; most KDF11-U's seem to have it. It apparently substituted a [[transceiver]] DS8641 [[gate]] at E52 (on page K6) for the receiver E70 (also on K6) connected to bus line 'AC LO', so that the KDF11-U could also ''drive'' AC LO.

			It starts with a cut of the short [[trace]] from E70p1 to the plated-through hole (PTH) next to it. A wire is then run from the PTH to E52p4 (the bus line on the transceiver), thereby connecting the latter directly to UNIBUS AC LO (on pin BF1).

			E52p5 (the transceiver's input) is connected to E73p13 (an DS8640 quad NOR used as a bus reciver), in the upper left corner of K2. That produces UNIBUS PB L NOR UNIBUS PA H - i.e. a [[parity]] error has been [[UNIBUS parity\|detected in memory]] - to which the response is apparently to power-fail the system!

			The incoming ACLO from the transceiver (E52p6) now has a wire going to a PTH next to E70p8. On the bottom side of the [[PCB]], there's a trace from that PTH that goes to E66p13 - which is the inverter (shown on K2) which converts BUF ACLO H to POWER OK H. So that answers the inevitable query about E70p1 being left floating after the etch cut: perhaps there's an etch cut somewhere that disconnected E66p13 from E70p2, so the former can now be driven by E52p6. (Theren is a trace from that latter PTH which dives under E70, and it's hard to see it, but it looks like it goes to E70p2.) It would be interesting to know what they did about the E70p2 -> E66p13 connection.

	==External links==		==External links==

Jnc: +Hardware details

2022-03-29T20:55:22Z

+Hardware details

← Older revision		Revision as of 20:55, 29 March 2022
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	[[Image:KDF11-U.jpg\|300px\|thumb\|right\|KDF11-U card with [[KTF11-A memory management chip\|KTF11-A]] and [[KEF11-A floating point chip\|KEF11-A]]]]		[[Image:KDF11-U.jpg\|300px\|thumb\|right\|KDF11-U card with [[KTF11-A memory management chip\|KTF11-A]] and [[KEF11-A floating point chip\|KEF11-A]]]]

	The '''KDF11-U''' is the [[PDP-11 architecture\|PDP-11]] [[Central Processing Unit\|CPU]] for the [[PDP-11/24]]; it ~~used the [[UNIBUS]], unlike the [[QBUS]] of the other [[KDF11 CPUs]]. It~~ was implemented as a single [[DEC card form factor\|hex]] [[printed circuit board\|board]], the KDF11-UA '''M7133'''~~, using~~ the same 'Fonz' [[F-11 chip set]] as the other KDF11 CPUs.		The '''KDF11-U''' is the [[PDP-11 architecture\|PDP-11]] [[Central Processing Unit\|CPU]] for the [[PDP-11/24]]; it was implemented as a single [[DEC card form factor\|hex]] [[printed circuit board\|board]], the KDF11-UA '''M7133'''. It used the same 'Fonz' [[F-11 chip set]] as the other KDF11 CPUs; however, it used the [[UNIBUS]], unlike the [[QBUS]] of the other [[KDF11 CPUs]].

	The board has seven 40-pin [[chip socket]]s for the [[integrated circuit\|chipset]] (including the [[KTF11-A memory management chip\|KTF11-A]] [[PDP-11 Memory Management\|memory ~~mapping~~]] and [[KEF11-A floating point chip\|KEF11-A]] [[floating point]] chips); it can also hold the double-width [[KEF11-B CIS chip]] 6-chip carrier implementing the [[PDP-11 Commercial Instruction Set]] (CIS) (not all KDF11 CPUs can hold this). In addition to the basic CPU functionality, the board also included two [[asynchronous serial line]]s (led out through the [[backplane]]).		The board has seven 40-pin [[Dual Inline Package\|DIP]] [[chip socket]]s for the [[integrated circuit\|chipset]] (including the [[KTF11-A memory management chip\|KTF11-A]] [[PDP-11 Memory Management\|memory management]] and [[KEF11-A floating point chip\|KEF11-A]] [[floating point]] chips); it can also hold the double-width [[KEF11-B CIS chip\|KEF11-B]] 6-chip carrier implementing the [[PDP-11 Commercial Instruction Set]] (CIS) (not all KDF11 CPUs can hold this). In addition to the basic CPU functionality, the board also included two [[asynchronous serial line]]s (led out through the [[backplane]]).

	There are two different versions of the KDF11-U; in the later M7133-YA, in order to reduce the cost, a number of individual ~~[[Dual Inline Package\|~~DIP]] [[integrated circuit\|chips]] were replaced with a pair of custom [[gate array]] chips, and the board was re-laid-out.		There are two different versions of the KDF11-U; in the later M7133-YA, in order to reduce the cost, a number of individual DIP [[integrated circuit\|chips]] were replaced with a pair of custom [[gate array]] chips, and the board was re-laid-out.

			The KDF11-U usually operates with the optional [[UNIBUS map]] board, the [[KT24 UNIBUS map option\|KT24]].

			==Hardware details==

			The technical documentation for the KDF11-U is not as complete as it could/should be. Some areas are covered here.

			===Voltages===

			The card mostly uses +5 [[volt]]s, but there is some use of +12V (produced from +15V by the 7812 [[voltage regulator]] at top center of page K12 of the KDF11-U Field Maintenance Print Set, 'SC, Interrupt, Voltage Regulation, Front Panel'): CHIP CLK generation (chip E16, top right center of page K1, 'Clock, State Decode'); [[EIA RS-232 serial line interface\|EIA]] interface chips (top left corner, page K12); F-11 chips (center of left side, page K13 of the prints, 'Fonz Chips'). There is also minimal use of -12V (produced from -15V at top center of page K12): [[Universal Asynchronous Receiver/Transmitter\|UART]] chips (top left corner, page K8, 'SLU 1, Baud', and page K9, 'Address Decode, MIB Buffer, SLU 2'); EIA interface chips (top left corner, page K12).

			===CPU clock===

			The CPU's main internal [[clock]] is a simple adjustable [[resistor\|R]]/[[capacitor\|C]] circuit (in the lower middle of page K1); the trim [[potentiometer]] that's part of it is physically just to the left of centre on the very upper edge of the board, and can be adjusted to set the clock speed 'properly'. See the note in the bottom left corner of page K14 ('Switches, Jumpers, Clock Setting' for the adjustment procedure (the clock should be 300 nsec). (The 2.7648 MHz [[crystal]] along the upper edge, just to its right, actually drives the [[baud rate]] generator for the built-in serial lines.)

			Section 4.2 ("Timimg") of the PDP-11/24 Technical Manual (below) covers all the various clocks used by the CPU section of the KDF11-U in some detail.

			===LED's===

			The board contains three [[Light Emitting Diode\|LED]]'s (along the upper edge), which provide [[diagnostic]] information. One (marked 'CLK') an indication that the CPU's main internal clock (on page K1 of the prints, in the very upper left corner) is running. The other two (left center, page K12) are driven by a write-only [[register]], and are used by diagnostic code in the [[bootstrap]] to indicate progress.

			The CLK LED is driven directly by the MCLK L internal [[signal]]; if that LED is not on, the CPU is not running. If either the bus ACLO or DCLO signals is asserted, MCLK L is off.

	==External links==		==External links==
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	* [http://www.bitsavers.org/pdf/dec/pdp11/1124/EK-11024-TM-001_PDP11_24_System_Technical_Manual_Jun81.pdf PDP-11/24 System Technical Manual] (EK-11024-TM-001) - the KDF11-U is covered in Chapters 3-5		* [http://www.bitsavers.org/pdf/dec/pdp11/1124/EK-11024-TM-001_PDP11_24_System_Technical_Manual_Jun81.pdf PDP-11/24 System Technical Manual] (EK-11024-TM-001) - the KDF11-U is covered in Chapters 3-5
	* [http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/dload/EK-11024-TM-003.pdf PDP-11/24 System Technical Manual] (EK-11024-TM-003) - the M7133-YA is documented in Appendix D		* [http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/dload/EK-11024-TM-003.pdf PDP-11/24 System Technical Manual] (EK-11024-TM-003) - the M7133-YA is documented in Appendix D
	* [http://www.bitsavers.org/pdf/dec/pdp11/1124/MP01018_1124schem_Aug80.pdf 11/24 Field Maintenance Print Set] - - KDF11-UA Field Maintenance Print Set (MP01028) is on pp. 145-167		* [http://www.bitsavers.org/pdf/dec/pdp11/1124/MP01018_1124schem_Aug80.pdf 11/24 Field Maintenance Print Set] - KDF11-UA Field Maintenance Print Set (MP01028) is on pp. 145-167

	~~{{Nav PDP-11}}~~

	[[Category:PDP-11 ~~Processors]]~~		[[Category: PDP-11 UNIBUS Processors]]
	~~[[Category:~~UNIBUS Processors]]

Jnc: /* External links */ typo, +clr copy

2022-01-15T15:47:07Z

External links: typo, +clr copy

← Older revision		Revision as of 15:47, 15 January 2022
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	==External links==		==External links==

	* [http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/dload/EK-11024-TM-003.pdf PDP-11/24 System Technical Manual] (EK-11024-TM-003) - ~~the KDF11-U is covered in Chapters -5;~~ the M7133-YA is documented in Appendix D		* [http://www.bitsavers.org/pdf/dec/pdp11/1124/EK-11024-TM-001_PDP11_24_System_Technical_Manual_Jun81.pdf PDP-11/24 System Technical Manual] (EK-11024-TM-001) - the KDF11-U is covered in Chapters 3-5
			* [http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/dload/EK-11024-TM-003.pdf PDP-11/24 System Technical Manual] (EK-11024-TM-003) - the M7133-YA is documented in Appendix D
	* [http://www.bitsavers.org/pdf/dec/pdp11/1124/MP01018_1124schem_Aug80.pdf 11/24 Field Maintenance Print Set] - - KDF11-UA Field Maintenance Print Set (MP01028) is on pp. 145-167		* [http://www.bitsavers.org/pdf/dec/pdp11/1124/MP01018_1124schem_Aug80.pdf 11/24 Field Maintenance Print Set] - - KDF11-UA Field Maintenance Print Set (MP01028) is on pp. 145-167

Jnc: /* External links */ typo

2022-01-15T11:10:17Z

External links: typo

← Older revision		Revision as of 11:10, 15 January 2022
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	* [http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/dload/EK-11024-TM-003.pdf PDP-11/24 System Technical Manual] (EK-11024-TM-003) - the KDF11-U is covered in Chapters -5; the M7133-YA is documented in Appendix D		* [http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/dload/EK-11024-TM-003.pdf PDP-11/24 System Technical Manual] (EK-11024-TM-003) - the KDF11-U is covered in Chapters -5; the M7133-YA is documented in Appendix D
	* [http://www.bitsavers.org/pdf/dec/pdp11/1124/MP01018_1124schem_Aug80.pdf xx Field Maintenance Print Set ] - - KDF11-UA Field Maintenance Print Set (MP01028) is on pp. 145-167		* [http://www.bitsavers.org/pdf/dec/pdp11/1124/MP01018_1124schem_Aug80.pdf 11/24 Field Maintenance Print Set] - - KDF11-UA Field Maintenance Print Set (MP01028) is on pp. 145-167

	{{Nav PDP-11}}		{{Nav PDP-11}}

Jnc: /* External links */ +FMPS, manual

2022-01-14T23:25:35Z

External links: +FMPS, manual

← Older revision		Revision as of 23:25, 14 January 2022
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	The board has seven 40-pin [[chip socket]]s for the [[integrated circuit\|chipset]] (including the [[KTF11-A memory management chip\|KTF11-A]] [[PDP-11 Memory Management\|memory mapping]] and [[KEF11-A floating point chip\|KEF11-A]] [[floating point]] chips); it can also hold the double-width [[KEF11-B CIS chip]] 6-chip carrier implementing the [[PDP-11 Commercial Instruction Set]] (CIS) (not all KDF11 CPUs can hold this). In addition to the basic CPU functionality, the board also included two [[asynchronous serial line]]s (led out through the [[backplane]]).		The board has seven 40-pin [[chip socket]]s for the [[integrated circuit\|chipset]] (including the [[KTF11-A memory management chip\|KTF11-A]] [[PDP-11 Memory Management\|memory mapping]] and [[KEF11-A floating point chip\|KEF11-A]] [[floating point]] chips); it can also hold the double-width [[KEF11-B CIS chip]] 6-chip carrier implementing the [[PDP-11 Commercial Instruction Set]] (CIS) (not all KDF11 CPUs can hold this). In addition to the basic CPU functionality, the board also included two [[asynchronous serial line]]s (led out through the [[backplane]]).

	There are two different versions of the KDF11-U; in the later M7133-YA ~~(documented in the manual EK-11024-TM-003, Appendix D)~~, in order to reduce the cost, a number of individual [[Dual Inline Package\|DIP]] [[integrated circuit\|chips]] were replaced with a pair of custom [[gate array]] chips, and the board was re-laid-out.		There are two different versions of the KDF11-U; in the later M7133-YA, in order to reduce the cost, a number of individual [[Dual Inline Package\|DIP]] [[integrated circuit\|chips]] were replaced with a pair of custom [[gate array]] chips, and the board was re-laid-out.

	{{PDP-11}}		==External links==

			* [http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/dload/EK-11024-TM-003.pdf PDP-11/24 System Technical Manual] (EK-11024-TM-003) - the KDF11-U is covered in Chapters -5; the M7133-YA is documented in Appendix D
			* [http://www.bitsavers.org/pdf/dec/pdp11/1124/MP01018_1124schem_Aug80.pdf xx Field Maintenance Print Set ] - - KDF11-UA Field Maintenance Print Set (MP01028) is on pp. 145-167

			{{Nav PDP-11}}

	[[Category:PDP-11 Processors]]		[[Category:PDP-11 Processors]]
	[[Category:UNIBUS Processors]]		[[Category:UNIBUS Processors]]

Jnc: link chips

2021-02-02T20:26:35Z

link chips

← Older revision		Revision as of 20:26, 2 February 2021
Line 1:		Line 1:
	[[Image:KDF11-U.jpg\|300px\|thumb\|right\|KDF11-U card with [[KTF11-A memory management chip\|KTF11-A]] and [[KEF11-A floating point chip\|KEF11-A]]]]		[[Image:KDF11-U.jpg\|300px\|thumb\|right\|KDF11-U card with [[KTF11-A memory management chip\|KTF11-A]] and [[KEF11-A floating point chip\|KEF11-A]]]]

	The '''KDF11-U''' is the [[PDP-11 architecture\|PDP-11]] [[Central Processing Unit\|CPU]] for the [[PDP-11/24]]; it used the [[UNIBUS]], unlike the [[QBUS]] of the other [[KDF11 CPUs]]. It was implemented as a single [[DEC card form factor\|hex]] ~~card~~, the KDF11-UA '''M7133''', using the same 'Fonz' [[F-11 chip set]] as the other KDF11 CPUs.		The '''KDF11-U''' is the [[PDP-11 architecture\|PDP-11]] [[Central Processing Unit\|CPU]] for the [[PDP-11/24]]; it used the [[UNIBUS]], unlike the [[QBUS]] of the other [[KDF11 CPUs]]. It was implemented as a single [[DEC card form factor\|hex]] [[printed circuit board\|board]], the KDF11-UA '''M7133''', using the same 'Fonz' [[F-11 chip set]] as the other KDF11 CPUs.

	~~In addition to~~ the ~~basic CPU functionality~~ (including [[PDP-11 Memory Management\|memory mapping]] and [[floating point]]), it also ~~included sockets to~~ hold a 6-chip carrier implementing the [[PDP-11 Commercial Instruction Set]] (CIS), ~~and~~ two [[asynchronous serial line]]s (led out through the [[backplane]]).		The board has seven 40-pin [[chip socket]]s for the [[integrated circuit\|chipset]] (including the [[KTF11-A memory management chip\|KTF11-A]] [[PDP-11 Memory Management\|memory mapping]] and [[KEF11-A floating point chip\|KEF11-A]] [[floating point]] chips); it can also hold the double-width [[KEF11-B CIS chip]] 6-chip carrier implementing the [[PDP-11 Commercial Instruction Set]] (CIS) (not all KDF11 CPUs can hold this). In addition to the basic CPU functionality, the board also included two [[asynchronous serial line]]s (led out through the [[backplane]]).

	There are two different versions of the KDF11-U; in the later M7133-YA (documented in the manual EK-11024-TM-003, Appendix D), in order to reduce the cost, a number of individual [[Dual Inline Package\|DIP]] [[integrated circuit\|chips]] were replaced with a pair of custom [[gate array]] chips, and the board was re-laid-out.		There are two different versions of the KDF11-U; in the later M7133-YA (documented in the manual EK-11024-TM-003, Appendix D), in order to reduce the cost, a number of individual [[Dual Inline Package\|DIP]] [[integrated circuit\|chips]] were replaced with a pair of custom [[gate array]] chips, and the board was re-laid-out.

← Older revision		Revision as of 03:24, 31 May 2022
Line 1:		Line 1:
	[[Image:KDF11-U.jpg\|300px\|thumb\|right\|KDF11-U card with [[KTF11-A memory management chip\|KTF11-A]] and [[KEF11-A floating point chip\|KEF11-A]]]]		[[Image:KDF11-U.jpg\|300px\|thumb\|right\|KDF11-U card with [[KTF11-A memory management chip\|KTF11-A]] and [[KEF11-A floating point chip\|KEF11-A]]]]

	The '''KDF11-U''' is the [[PDP-11 architecture\|PDP-11]] [[Central Processing Unit\|CPU]] for the [[PDP-11/24]]; it was implemented as a single [[DEC card form factor\|hex]] [[printed circuit board\|board]], the KDF11-UA '''M7133'''. It used the same 'Fonz' [[F-11 chip set]] as the other KDF11 CPUs; however, it used the [[UNIBUS]], unlike the [[QBUS]] of the other [[KDF11 CPUs]].		The '''KDF11-U''' is the [[PDP-11 architecture\|PDP-11]] [[Central Processing Unit\|CPU]] for the [[PDP-11/24]]; it was implemented as a single [[DEC card form factor\|hex]] [[printed circuit board\|board]], the KDF11-UA '''M7133'''. It used the same 'Fonz' [[F-11 chip set]] as the other KDF11 CPUs; however, it used the [[UNIBUS]], unlike the [[QBUS]] of the other [[KDF11 CPUs]]. It plugs into a custom slot in the likewise custom PDP-11/24 [[backplane]] ([[DEC part number]] 54-13817, assembly 70-16905).

	The board has seven 40-pin [[Dual Inline Package\|DIP]] [[chip socket]]s for the [[integrated circuit\|chipset]] (including the [[KTF11-A memory management chip\|KTF11-A]] [[PDP-11 Memory Management\|memory management]] and [[KEF11-A floating point chip\|KEF11-A]] [[floating point]] chips); it can also hold the double-width [[KEF11-B CIS chip\|KEF11-B]] 6-chip carrier implementing the [[PDP-11 Commercial Instruction Set]] (CIS) (not all KDF11 CPUs can hold this). In addition to the basic CPU functionality, the board also included two [[asynchronous serial line]]s (led out through the [[backplane]]).		The board has seven 40-pin [[Dual Inline Package\|DIP]] [[chip socket]]s for the [[integrated circuit\|chipset]] (including the [[KTF11-A memory management chip\|KTF11-A]] [[PDP-11 Memory Management\|memory management]] and [[KEF11-A floating point chip\|KEF11-A]] [[floating point]] chips); it can also hold the double-width [[KEF11-B CIS chip\|KEF11-B]] 6-chip carrier implementing the [[PDP-11 Commercial Instruction Set]] (CIS) (not all KDF11 CPUs can hold this). In addition to the basic CPU functionality, the board also included two [[asynchronous serial line]]s (led out through the [[backplane]]).

← Older revision		Revision as of 01:20, 31 May 2022
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	The incoming ACLO from the transceiver (E52p6) now has a wire going to a PTH next to E70p8. On the bottom side of the [[printed circuit board\|PCB]], there's a trace from that PTH to E66p13 - which is the [[inverter]] (shown on K2) which converts BUF ACLO H to POWER OK H. So that answers the inevitable query about E70p1 (and its output, E70p2) being left floating after the etch cut: perhaps there's an etch cut somewhere that disconnected E66p13 from E70p2, so the former can now be driven by E52p6. (There is a trace from that latter PTH which dives under E70, and although it's hard to see it, it looks like it goes to E70p2.) It would be interesting to know what they did about the E70p2 -> E66p13 connection.		The incoming ACLO from the transceiver (E52p6) now has a wire going to a PTH next to E70p8. On the bottom side of the [[printed circuit board\|PCB]], there's a trace from that PTH to E66p13 - which is the [[inverter]] (shown on K2) which converts BUF ACLO H to POWER OK H. So that answers the inevitable query about E70p1 (and its output, E70p2) being left floating after the etch cut: perhaps there's an etch cut somewhere that disconnected E66p13 from E70p2, so the former can now be driven by E52p6. (There is a trace from that latter PTH which dives under E70, and although it's hard to see it, it looks like it goes to E70p2.) It would be interesting to know what they did about the E70p2 -> E66p13 connection.

			==See also==

			* [[KDF11-U CPU pinout]]

	==External links==		==External links==

← Older revision		Revision as of 20:26, 2 February 2021
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	[[Image:KDF11-U.jpg\|300px\|thumb\|right\|KDF11-U card with [[KTF11-A memory management chip\|KTF11-A]] and [[KEF11-A floating point chip\|KEF11-A]]]]		[[Image:KDF11-U.jpg\|300px\|thumb\|right\|KDF11-U card with [[KTF11-A memory management chip\|KTF11-A]] and [[KEF11-A floating point chip\|KEF11-A]]]]

	The '''KDF11-U''' is the [[PDP-11 architecture\|PDP-11]] [[Central Processing Unit\|CPU]] for the [[PDP-11/24]]; it used the [[UNIBUS]], unlike the [[QBUS]] of the other [[KDF11 CPUs]]. It was implemented as a single [[DEC card form factor\|hex]] ~~card~~, the KDF11-UA '''M7133''', using the same 'Fonz' [[F-11 chip set]] as the other KDF11 CPUs.		The '''KDF11-U''' is the [[PDP-11 architecture\|PDP-11]] [[Central Processing Unit\|CPU]] for the [[PDP-11/24]]; it used the [[UNIBUS]], unlike the [[QBUS]] of the other [[KDF11 CPUs]]. It was implemented as a single [[DEC card form factor\|hex]] [[printed circuit board\|board]], the KDF11-UA '''M7133''', using the same 'Fonz' [[F-11 chip set]] as the other KDF11 CPUs.

	~~In addition to~~ the ~~basic CPU functionality~~ (including [[PDP-11 Memory Management\|memory mapping]] and [[floating point]]), it also ~~included sockets to~~ hold a 6-chip carrier implementing the [[PDP-11 Commercial Instruction Set]] (CIS), ~~and~~ two [[asynchronous serial line]]s (led out through the [[backplane]]).		The board has seven 40-pin [[chip socket]]s for the [[integrated circuit\|chipset]] (including the [[KTF11-A memory management chip\|KTF11-A]] [[PDP-11 Memory Management\|memory mapping]] and [[KEF11-A floating point chip\|KEF11-A]] [[floating point]] chips); it can also hold the double-width [[KEF11-B CIS chip]] 6-chip carrier implementing the [[PDP-11 Commercial Instruction Set]] (CIS) (not all KDF11 CPUs can hold this). In addition to the basic CPU functionality, the board also included two [[asynchronous serial line]]s (led out through the [[backplane]]).

	There are two different versions of the KDF11-U; in the later M7133-YA (documented in the manual EK-11024-TM-003, Appendix D), in order to reduce the cost, a number of individual [[Dual Inline Package\|DIP]] [[integrated circuit\|chips]] were replaced with a pair of custom [[gate array]] chips, and the board was re-laid-out.		There are two different versions of the KDF11-U; in the later M7133-YA (documented in the manual EK-11024-TM-003, Appendix D), in order to reduce the cost, a number of individual [[Dual Inline Package\|DIP]] [[integrated circuit\|chips]] were replaced with a pair of custom [[gate array]] chips, and the board was re-laid-out.