KDF11 CPUs - Revision history

Jnc: /* External links */ +DCF11 Processors

2025-05-31T13:01:05Z

‎External links: +DCF11 Processors

Jnc: /* Further reading */ +Wake-up Circuit Implementations

2024-07-29T15:03:09Z

‎Further reading: +Wake-up Circuit Implementations

Jnc: /* Further reading */ +LSI-11/23 I/O Page Addressing

2024-07-29T11:08:51Z

‎Further reading: +LSI-11/23 I/O Page Addressing

Jnc: /* Further reading */ +Peripheral Compatibility with 11/23 Systems

2024-07-29T11:02:26Z

‎Further reading: +Peripheral Compatibility with 11/23 Systems

Jnc: /* Further reading */ +Parity Memory in LSI-11/23 Systems

2024-07-27T23:58:38Z

‎Further reading: +Parity Memory in LSI-11/23 Systems

Jnc: /* Further reading */ +System Differences - LSI-11 vs. LSI-11/23

2024-07-27T23:35:57Z

‎Further reading: +System Differences - LSI-11 vs. LSI-11/23

Jnc: /* Further reading */ +LSI-11/23 Processor Differences

2024-07-25T18:50:47Z

‎Further reading: +LSI-11/23 Processor Differences

Jnc: /* Further reading */ +LSI-11/23 Instruction Timing

2024-07-25T13:21:02Z

‎Further reading: +LSI-11/23 Instruction Timing

Jnc: More specific cats

2022-03-29T11:49:15Z

More specific cats

Jnc: KDF11-U

2021-11-19T20:47:02Z

KDF11-U

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 * ''Parity Memory in LSI-11/23 Systems'', MicroNote #052
 * ''Wake-up Circuit Implementations'', MicroNote #085
 [[Category: PDP-11 UNIBUS Processors]]
 [[Category: PDP-11 QBUS Processors]]

@@ Line 30: / Line 30: @@
 * ''Peripheral Compatibility with 11/23 Systems'', MicroNote #072
 * ''Parity Memory in LSI-11/23 Systems'', MicroNote #052
 [[Category: PDP-11 UNIBUS Processors]]
 [[Category: PDP-11 QBUS Processors]]

@@ Line 26: / Line 26: @@
 * ''LSI-11/23 Instruction Timing'', [[MicroNote]] #048
 * ''LSI-11/23 Processor Differences'', MicroNote #078
 * ''System Differences - LSI-11 vs. LSI-11/23'', MicroNote #049
 * ''Peripheral Compatibility with 11/23 Systems'', MicroNote #072
 [[Category: PDP-11 UNIBUS Processors]]
 [[Category: PDP-11 QBUS Processors]]

@@ Line 28: / Line 28: @@
 * ''Parity Memory in LSI-11/23 Systems'', MicroNote #052
 * ''System Differences - LSI-11 vs. LSI-11/23'', MicroNote #049
 [[Category: PDP-11 UNIBUS Processors]]
 [[Category: PDP-11 QBUS Processors]]

@@ Line 26: / Line 26: @@
 * ''LSI-11/23 Instruction Timing'', [[MicroNote]] #048
 * ''LSI-11/23 Processor Differences'', MicroNote #078
 * ''System Differences - LSI-11 vs. LSI-11/23'', MicroNote #049
 [[Category: PDP-11 UNIBUS Processors]]
 [[Category: PDP-11 QBUS Processors]]

@@ Line 1: / Line 1: @@
 The '''KDF11 CPUs''' are single-[[printed circuit board|board]] [[PDP-11]] [[Central Processing Unit|CPUs]] which all use the 'Fonz' [[F-11 chip set]]:
-*[[KDF11-A CPU]] - M8186 - [[QBUS]] [[DEC card form factor|dual]]-width CPU used in the [[PDP-11/23]]
+* [[KDF11-A CPU]] - M8186 - [[QBUS]] [[DEC card form factor|dual]]-width CPU used in the [[PDP-11/23]]
-*[[KDF11-B CPU]] - M8189 - QBUS quad-width CPU used in the [[PDP-11/23_PLUS|PDP-11/23+]]
+* [[KDF11-B CPU]] - M8189 - QBUS quad-width CPU used in the [[PDP-11/23_PLUS|PDP-11/23+]]
-*[[KDF11-U CPU]] - M7133 - [[UNIBUS]] hex-width CPU used in the [[PDP-11/24]]
+* [[KDF11-U CPU]] - M7133 - [[UNIBUS]] hex-width CPU used in the [[PDP-11/24]]
-The basic [[clock]] µcycle is 300 nsec; simple [[register]]-register [[instruction]]s (e.g. MOV, ADD, etc) took 1.7 µseconds (1.2 µseconds on the KDF11-U). Depending on the [[operand]] [[PDP-11 architecture#Operands|modes]] used in a particular instruction, and the [[main memory]] speed (with the [[asynchronous]] QBUS), that could add up to roughly 8.5 µseconds (4.2 µseconds on the KDF11-U) to that basic time. (The extra time is roughly linear in the number of [[memory cycle]]s, at 1.2 µseconds (0.8 µseconds on the KDF11-U) per cycle - PDP-11 instructions could add up to 6 additional memory cycles per instruction, above the 1 needed to [[fetch]] the basic instruction.)
+The basic [[clock]] µcycle is 300 nsec; simple [[register]]-register [[instruction]]s (e.g. MOV, ADD, etc) took 1.7 µseconds (1.2 µseconds on the KDF11-U). Depending on the [[operand]] [[PDP-11 architecture#Operands|modes]] used in a particular instruction, and the [[main memory]] speed (with the [[asynchronous]] QBUS), that could add up to roughly 8.5 µseconds (4.2 µseconds on the KDF11-U) to that basic time. (The extra time is roughly linear in the number of [[memory cycle]]s, at roughly 1.2 µseconds (0.8 µseconds on the KDF11-U) per cycle - PDP-11 instructions could add up to 6 additional memory cycles per instruction, above the 1 needed to [[fetch]] the basic instruction.)
 Like the [[LSI-11 CPUs|LSI-11]] models, as a cost-reduction measure they do not have a [[front panel]] to control them; instead, when the CPU is halted, specialized [[microcode]] used the main [[asynchronous serial line]] as a operating console. The command set is named Octal Debugging Technique ([[QBUS CPU ODT|ODT]]); there are commands to read and write [[main memory]], start the CPU, etc.
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 * [[KDJ11 CPUs]]
-{{PDP-11}}
+[[Category: PDP-11 UNIBUS Processors]]
+[[Category: PDP-11 QBUS Processors]]

← Older revision		Revision as of 20:47, 19 November 2021
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	[[Category: PDP-11 Processors]]		[[Category: PDP-11 Processors]]
	[[Category: QBUS Processors]]		[[Category: QBUS Processors]]
		+	[[Category: UNIBUS Processors]]