KDJ11 CPUs - Revision history

Jnc: /* External links */ original at Frain Research went offline; add reference to online mirror

2025-05-31T12:10:31Z

External links: original at Frain Research went offline; add reference to online mirror

← Older revision		Revision as of 12:10, 31 May 2025
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	==External links==		==External links==

	* [http://web.frainresearch.org:8080/projects/pdp-11/dcj11.php DCJ11 Processors]		* [http://web.frainresearch.org:8080/projects/pdp-11/dcj11.php DCJ11 Processors] (mirrored [https://electrickery.nl/comp/pdp11_23plus/frain.rsx11m.io/dcj11.php here])

	[[Category: PDP-11 QBUS Processors]]		[[Category: PDP-11 QBUS Processors]]

Jnc: KDJ11-B also used in the PDP-11/73

2023-02-21T12:32:16Z

KDJ11-B also used in the PDP-11/73

← Older revision		Revision as of 12:32, 21 February 2023
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	* [[KDJ11-A CPU]] - M8192 - [[QBUS]] [[DEC card form factor\|dual]]-width CPU		* [[KDJ11-A CPU]] - M8192 - [[QBUS]] [[DEC card form factor\|dual]]-width CPU
	* [[KDJ11-B CPU]] - M8190 - QBUS quad-width CPU used in the [[PDP-11/83]] and [[PDP-11/84]]		* [[KDJ11-B CPU]] - M8190 - QBUS quad-width CPU used in the [[PDP-11/73]], [[PDP-11/83]] and [[PDP-11/84]]
	* [[KDJ11-D CPU]] - M7554 - QBUS quad-width CPU used in the [[PDP-11/53]]		* [[KDJ11-D CPU]] - M7554 - QBUS quad-width CPU used in the [[PDP-11/53]]
	* [[KDJ11-E CPU]] - M8981 - QBUS quad-width CPU used in the [[PDP-11/93]] and [[PDP-11/94]]		* [[KDJ11-E CPU]] - M8981 - QBUS quad-width CPU used in the [[PDP-11/93]] and [[PDP-11/94]]

Jnc: typo

2022-03-29T11:44:50Z

typo

← Older revision		Revision as of 11:44, 29 March 2022
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	* [http://web.frainresearch.org:8080/projects/pdp-11/dcj11.php DCJ11 Processors]		* [http://web.frainresearch.org:8080/projects/pdp-11/dcj11.php DCJ11 Processors]

	[[Category: ~~QBUS~~ PDP-11 Processors]]		[[Category: PDP-11 QBUS Processors]]

Jnc: /* See also */ +

2022-03-29T11:43:55Z

Jnc: new more-specific cat

2022-03-29T11:40:22Z

new more-specific cat

← Older revision		Revision as of 11:40, 29 March 2022
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	* [http://web.frainresearch.org:8080/projects/pdp-11/dcj11.php DCJ11 Processors]		* [http://web.frainresearch.org:8080/projects/pdp-11/dcj11.php DCJ11 Processors]

	[[Category: PDP-11 ~~Processors]]~~		[[Category: QBUS PDP-11 Processors]]
	~~[[Category: QBUS~~ Processors]]

Jnc: /* Floating point */ no FPJ11 on the KDJ11-D

2022-03-29T08:37:50Z

Floating point: no FPJ11 on the KDJ11-D

← Older revision		Revision as of 08:37, 29 March 2022
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	==Floating point==		==Floating point==

	All the KDJ11 CPUs except early revisions of the KDJ11-A CPU have two choices for [[floating point]] support (full [[FP11 floating point]]): the base DCJ11 [[integrated circuit\|chip]], which implements floating point using [[microcode]]; and an optional, higher-performance separate dedicated chip, the [[FPJ11 floating point accelerator]].		All the KDJ11 CPUs except early revisions of the KDJ11-A CPU and the KDJ11-D have two choices for [[floating point]] support (full [[FP11 floating point]]): the base DCJ11 [[integrated circuit\|chip]], which implements floating point using [[microcode]]; and an optional, higher-performance separate dedicated chip, the [[FPJ11 floating point accelerator]].

	(The issue with the early KDJ11-A is that early revisions have bugs in their [[gate array]] chips which prevent correct operation of the FPJ11.)		(The issue with the early KDJ11-A is that early revisions have bugs in their [[gate array]] chips which prevent correct operation of the FPJ11.)

Jnc: +KDJ11-D, halt details

2022-03-29T08:35:34Z

+KDJ11-D, halt details

← Older revision		Revision as of 08:35, 29 March 2022
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	There are several single-board [[PDP-11]] [[Central Processing Unit\|CPUs]] which all use the 'Jaws' [[J-11 chipset]]:		There are several single-board [[PDP-11]] [[Central Processing Unit\|CPUs]] which all use the 'Jaws' [[J-11 chipset]]:

	*[[KDJ11-A CPU]] - M8192 - [[QBUS]] [[DEC card form factor\|dual]]-width CPU		* [[KDJ11-A CPU]] - M8192 - [[QBUS]] [[DEC card form factor\|dual]]-width CPU
	*[[KDJ11-B CPU]] - M8190 - QBUS quad-width CPU used in the [[PDP-11/83]] and [[PDP-11/84]]		* [[KDJ11-B CPU]] - M8190 - QBUS quad-width CPU used in the [[PDP-11/83]] and [[PDP-11/84]]
	*[[KDJ11-E CPU]] - M8981 - QBUS quad-width CPU used in the [[PDP-11/93]] and [[PDP-11/94]]		* [[KDJ11-D CPU]] - M7554 - QBUS quad-width CPU used in the [[PDP-11/53]]
			* [[KDJ11-E CPU]] - M8981 - QBUS quad-width CPU used in the [[PDP-11/93]] and [[PDP-11/94]]

	==Floating point==		==Floating point==
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	==ODT and the cache==		==ODT and the cache==

	The J-11 chip set includes [[microcode]] which provides 'front panel' functionality named '[[QBUS CPU ODT\|ODT]]'; the ability to read and write to [[main memory]], start the processor, etc. Unlike the ODT in the [[KDF11 CPUs]], which only supported 18-bit addressing, the KDJ11's do not have this limitation.		The J-11 chip set includes microcode which provides '[[front panel]]' functionality named '[[QBUS CPU ODT\|ODT]]', which runs when the CPU is [[halt]]ed: the ability to read and write to [[main memory]], start the processor, etc. Unlike the ODT in the [[KDF11 CPUs]], which only supported 18-bit addressing, the KDJ11's do not have this limitation.

	Note, however, that the KDJ11-A and KDJ11-B, which have CPU [[cache]]s, power up with the cache enabled, even for ODT. So, if the user writes some data into a given memory location using ODT, and then reads it back, they will get the correct data even if that memory location is faulty - the CPU is getting the (correct) data from the cache.		Note, however, that the KDJ11-A and KDJ11-B, which have CPU [[cache]]s, power up with the cache enabled, even for ODT. So, if the user writes some data into a given memory location using ODT, and then reads it back, they will get the correct data even if that memory location is faulty - the CPU is getting the (correct) data from the cache.
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	* [http://web.frainresearch.org:8080/projects/pdp-11/dcj11.php DCJ11 Processors]		* [http://web.frainresearch.org:8080/projects/pdp-11/dcj11.php DCJ11 Processors]

	~~{{PDP-11}}~~

	[[Category: PDP-11 Processors]]		[[Category: PDP-11 Processors]]
	[[Category: QBUS Processors]]		[[Category: QBUS Processors]]

Jnc: /* External links */ +good page

2021-12-27T13:17:08Z

External links: +good page

← Older revision		Revision as of 13:17, 27 December 2021
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	* uNote #025, "FPJ11-AA Compatibility with the LSI-11/73 (KDJ11-A)", 28 April 1985		* uNote #025, "FPJ11-AA Compatibility with the LSI-11/73 (KDJ11-A)", 28 April 1985

			==External links==

			* [http://web.frainresearch.org:8080/projects/pdp-11/dcj11.php DCJ11 Processors]

	{{PDP-11}}		{{PDP-11}}

Jnc: /* Code in PARs */ typo

2021-10-23T19:56:03Z

Code in PARs: typo

← Older revision		Revision as of 19:56, 23 October 2021
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	==Code in PARs==		==Code in PARs==

	One commonly used diagnostic 'trick' is to store very small test programs in the Page Address Registers of the [[PDP-11 Memory Management]] unit. This is typically used for short 'oscilliscope loops', either to debug a memory card when isn't any working memory plugged in, or when there is a desire to avoid 'contaminating' the bus with [[instruction]] fetch cycles.		One commonly used diagnostic 'trick' is to store very small test programs in the Page Address Registers of the [[PDP-11 Memory Management]] unit. This is typically used for short 'oscilliscope loops', either to debug a memory card when there isn't any working memory plugged in, or when there is a desire to avoid 'contaminating' the bus with [[instruction]] [[fetch]] cycles.

	However, this does not work on the KDJ11 processors. The CPU cannot execute [[object code\|code]] from the PARs; it gets a [[NXM]] [[trap]] on attempts to do so.		However, this does not work on the KDJ11 processors. The CPU cannot execute [[object code\|code]] from the PARs; it gets a [[NXM]] [[trap]] on attempts to do so.

Jnc: /* Floating point */ +link

2020-01-05T20:29:26Z

Floating point: +link

← Older revision		Revision as of 20:29, 5 January 2020
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	==Floating point==		==Floating point==

	All the KDJ11 CPUs except early revisions of the KDJ11-A CPU have two choices for [[floating point]] support (full [[FP11 floating point]]): the base DCJ11 chip, which implements floating point using [[microcode]]; and an optional higher-performance separate dedicated chip, the [[FPJ11 floating point accelerator]].		All the KDJ11 CPUs except early revisions of the KDJ11-A CPU have two choices for [[floating point]] support (full [[FP11 floating point]]): the base DCJ11 [[integrated circuit\|chip]], which implements floating point using [[microcode]]; and an optional, higher-performance separate dedicated chip, the [[FPJ11 floating point accelerator]].

	(The issue with the KDJ11-A is that early revisions have bugs in their [[gate array]] ~~[[chip]]s~~ which prevent correct operation of the FPJ11.)		(The issue with the early KDJ11-A is that early revisions have bugs in their [[gate array]] chips which prevent correct operation of the FPJ11.)

	==ODT and the cache==		==ODT and the cache==

← Older revision		Revision as of 11:43, 29 March 2022
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	However, this does not work on the KDJ11 processors. The CPU cannot execute [[object code\|code]] from the PARs; it gets a [[NXM]] [[trap]] on attempts to do so.		However, this does not work on the KDJ11 processors. The CPU cannot execute [[object code\|code]] from the PARs; it gets a [[NXM]] [[trap]] on attempts to do so.

			==See also==

			* [[LSI-11 CPUs]]
			* [[KDF11 CPUs]]

	==Further reading==		==Further reading==