KI10 - Revision history

Jnc: /* External links */ trim URL

2025-04-22T17:50:56Z

External links: trim URL

← Older revision		Revision as of 17:50, 22 April 2025
Line 46:		Line 46:
	* [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V1_Oct74.pdf PDP-10 module schematics Vol.1]		* [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V1_Oct74.pdf PDP-10 module schematics Vol.1]
	* [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V2_Oct74.pdf PDP-10 module schematics Vol.2]		* [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V2_Oct74.pdf PDP-10 module schematics Vol.2]
	* [https://onlineonly.christies.com/s/firsts-history-computing-paul-g-allen-collection/dec-pdp-10-ki10-mainframe-computer-125/230064~~?ldp_breadcrumb=back~~ DEC PDP-10 KI10 mainframe computer] - one from [[Paul Allen]]'s collection at the [[Living Computer Museum\|LCM]], includes several images		* [https://onlineonly.christies.com/s/firsts-history-computing-paul-g-allen-collection/dec-pdp-10-ki10-mainframe-computer-125/230064 DEC PDP-10 KI10 mainframe computer] - one from [[Paul Allen]]'s collection at the [[Living Computer Museum\|LCM]], includes several images

	[[Category: PDP-10 Processors]]		[[Category: PDP-10 Processors]]

Jnc: /* External links */ +one from Paul Allen's collection at the LCM

2025-04-22T12:53:45Z

External links: +one from Paul Allen's collection at the LCM

← Older revision		Revision as of 12:53, 22 April 2025
Line 38:		Line 38:
	The KI10 Memory Bus is slightly different from that of the [[KA10]]; KA10-style memories can be used on a KI10, but require use of a [[KI10-M Memory Bus Adapter]] (see Section 6.7 of the KI10 Central Processor Maintenance Manual).		The KI10 Memory Bus is slightly different from that of the [[KA10]]; KA10-style memories can be used on a KI10, but require use of a [[KI10-M Memory Bus Adapter]] (see Section 6.7 of the KI10 Central Processor Maintenance Manual).

			<br clear=all>
	==External links==		==External links==

Line 45:		Line 46:
	* [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V1_Oct74.pdf PDP-10 module schematics Vol.1]		* [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V1_Oct74.pdf PDP-10 module schematics Vol.1]
	* [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V2_Oct74.pdf PDP-10 module schematics Vol.2]		* [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V2_Oct74.pdf PDP-10 module schematics Vol.2]
			* [https://onlineonly.christies.com/s/firsts-history-computing-paul-g-allen-collection/dec-pdp-10-ki10-mainframe-computer-125/230064?ldp_breadcrumb=back DEC PDP-10 KI10 mainframe computer] - one from [[Paul Allen]]'s collection at the [[Living Computer Museum\|LCM]], includes several images

	[[Category: PDP-10 Processors]]		[[Category: PDP-10 Processors]]

Jnc: /* Busses */ KA10-style memories require use of a KI10-M Memory Bus Adapter

2023-11-05T11:23:28Z

Busses: KA10-style memories require use of a KI10-M Memory Bus Adapter

← Older revision		Revision as of 11:23, 5 November 2023
Line 34:		Line 34:
	[[Image:KBusQCUnlatched.jpg\|250px\|thumb\|right\|Memory bus Quick Latch connector (in unlatched position)]]		[[Image:KBusQCUnlatched.jpg\|250px\|thumb\|right\|Memory bus Quick Latch connector (in unlatched position)]]

	Although the KI10 [[CPU]] provided two each of [[PDP-10 Memory Bus]] and [[PDP-10 I/O Bus]] connectors (Quick Latch connectors for the former), there is only one bus of each type; the two connectors are provided for physical cabling convenience (left and right of the CPU cabinet).		Although the KI10 [[Central Processing Unit\|CPU]] provided two each of [[PDP-10 Memory Bus]] and [[PDP-10 I/O Bus]] connectors (Quick Latch connectors for the former), there is only one bus of each type; the two connectors are provided for physical cabling convenience (left and right of the CPU cabinet).

			The KI10 Memory Bus is slightly different from that of the [[KA10]]; KA10-style memories can be used on a KI10, but require use of a [[KI10-M Memory Bus Adapter]] (see Section 6.7 of the KI10 Central Processor Maintenance Manual).

	==External links==		==External links==

Jnc: Small FLIP CHIPs

2023-06-09T08:02:43Z

Small FLIP CHIPs

← Older revision		Revision as of 08:02, 9 June 2023
Line 22:		Line 22:
	[[Image:Sys37a.jpg\|thumb\|300px\|left\|KI10 at Tymshare]]		[[Image:Sys37a.jpg\|thumb\|300px\|left\|KI10 at Tymshare]]

	The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[transistor-transistor logic\|TTL]] [[integrated circuit\|chip]]s, on [[FLIP CHIP]] cards.		The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[transistor-transistor logic\|TTL]] [[integrated circuit\|chip]]s, on small [[FLIP CHIP]] cards.

	It was the first PDP-10 model to provide [[paging]] in its as-shipped form, with 512-[[word]] pages. It was initially released in a single-[[central processing unit\|CPU]] version (DECsystem-1060 and -1070); a two-CPU version (DECsystem-1077) was released later.		It was the first PDP-10 model to provide [[paging]] in its as-shipped form, with 512-[[word]] pages. It was initially released in a single-[[central processing unit\|CPU]] version (DECsystem-1060 and -1070); a two-CPU version (DECsystem-1077) was released later.

Jnc: /* Busses */ links to new pages

2022-10-25T16:16:30Z

Busses: links to new pages

← Older revision		Revision as of 16:16, 25 October 2022
Line 34:		Line 34:
	[[Image:KBusQCUnlatched.jpg\|250px\|thumb\|right\|Memory bus Quick Latch connector (in unlatched position)]]		[[Image:KBusQCUnlatched.jpg\|250px\|thumb\|right\|Memory bus Quick Latch connector (in unlatched position)]]

	Although the KI10 [[CPU]] provided two each of ~~memory bus~~ and I/O ~~bus~~ connectors (Quick Latch connectors for the former), there is only one bus of each type; the two connectors are provided for physical cabling convenience (left and right of the CPU cabinet).		Although the KI10 [[CPU]] provided two each of [[PDP-10 Memory Bus]] and [[PDP-10 I/O Bus]] connectors (Quick Latch connectors for the former), there is only one bus of each type; the two connectors are provided for physical cabling convenience (left and right of the CPU cabinet).

	==External links==		==External links==

Jnc: use new inst speed

2022-08-10T11:06:52Z

use new inst speed

← Older revision		Revision as of 11:06, 10 August 2022
Line 10:		Line 10:
	\| virtual address = 18 bits		\| virtual address = 18 bits
	\| logic type = [[transistor-transistor logic\|TTL]] [[IC]]s		\| logic type = [[transistor-transistor logic\|TTL]] [[IC]]s
	\| design type = clocked synchronous		\| design type = clocked synchronous
	\| ~~clock~~ speed = 1 μsec		\| instruction speed = 1 μsec
	\| memory speed = 1.0 μsec (fast), 1.8 μsec (slow)		\| memory speed = 1.0 μsec (fast), 1.8 μsec (slow)
	\| memory mgmt = [[paging]], 512-word pages		\| memory mgmt = [[paging]], 512-word pages
Line 34:		Line 34:
	[[Image:KBusQCUnlatched.jpg\|250px\|thumb\|right\|Memory bus Quick Latch connector (in unlatched position)]]		[[Image:KBusQCUnlatched.jpg\|250px\|thumb\|right\|Memory bus Quick Latch connector (in unlatched position)]]

	Although the KI10 [[CPU]] provided two each memory bus and I/O bus connectors (Quick Latch connectors for the former), there is only one bus of each type; the two connectors are provided for physical cabling convenience (left and right of the CPU cabinet).		Although the KI10 [[CPU]] provided two each of memory bus and I/O bus connectors (Quick Latch connectors for the former), there is only one bus of each type; the two connectors are provided for physical cabling convenience (left and right of the CPU cabinet).

	==External links==		==External links==

Larsbrinkhoff: Very rarely called "PDP-10I".

2022-01-11T06:38:24Z

Very rarely called "PDP-10I".

← Older revision		Revision as of 06:38, 11 January 2022
Line 27:		Line 27:

	It was used in later [[DECsystem-10]] models, running [[TOPS-10]]. Via a series of kludges, it was also possible to run [[TENEX]] on the as-shipped hardware.		It was used in later [[DECsystem-10]] models, running [[TOPS-10]]. Via a series of kludges, it was also possible to run [[TENEX]] on the as-shipped hardware.

			A few documents refer to the KI10-based system as PDP-10I.

	==Busses==		==Busses==

Jnc: /* External links */ +PDP-10 module schematics

2022-01-09T20:36:58Z

External links: +PDP-10 module schematics

← Older revision		Revision as of 20:36, 9 January 2022
Line 39:		Line 39:
	** [http://www.bitsavers.org/pdf/dec/pdp10/KI10/A_Document_On_The_KI10_Apr73.pdf A Document On The KI10]		** [http://www.bitsavers.org/pdf/dec/pdp10/KI10/A_Document_On_The_KI10_Apr73.pdf A Document On The KI10]
	** [http://www.bitsavers.org/pdf/dec/pdp10/KI10/KI10ProcMaintMan.pdf KI10 Central Processor Maintenance Manual]		** [http://www.bitsavers.org/pdf/dec/pdp10/KI10/KI10ProcMaintMan.pdf KI10 Central Processor Maintenance Manual]
			* [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V1_Oct74.pdf PDP-10 module schematics Vol.1]
			* [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V2_Oct74.pdf PDP-10 module schematics Vol.2]

	[[Category: PDP-10 Processors]]		[[Category: PDP-10 Processors]]

Jnc: bus details

2021-10-12T18:24:37Z

bus details

← Older revision		Revision as of 18:24, 12 October 2021
Line 23:		Line 23:

	The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[transistor-transistor logic\|TTL]] [[integrated circuit\|chip]]s, on [[FLIP CHIP]] cards.		The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[transistor-transistor logic\|TTL]] [[integrated circuit\|chip]]s, on [[FLIP CHIP]] cards.

			It was the first PDP-10 model to provide [[paging]] in its as-shipped form, with 512-[[word]] pages. It was initially released in a single-[[central processing unit\|CPU]] version (DECsystem-1060 and -1070); a two-CPU version (DECsystem-1077) was released later.

	It was used in later [[DECsystem-10]] models, running [[TOPS-10]]. Via a series of kludges, it was also possible to run [[TENEX]] on the as-shipped hardware.		It was used in later [[DECsystem-10]] models, running [[TOPS-10]]. Via a series of kludges, it was also possible to run [[TENEX]] on the as-shipped hardware.

	~~It was the first PDP-10 model to provide~~ [[~~paging]]~~ in ~~its as-shipped form, with 512-[[word~~]] ~~pages. It was initially released in a single-~~[[~~central processing unit\|~~CPU]] ~~version~~ (~~DECsystem-1060 and -1070~~); a two-CPU ~~version (DECsystem-1077~~) ~~was released later~~.		==Busses==

			[[Image:KBusQCUnlatched.jpg\|250px\|thumb\|right\|Memory bus Quick Latch connector (in unlatched position)]]

			Although the KI10 [[CPU]] provided two each memory bus and I/O bus connectors (Quick Latch connectors for the former), there is only one bus of each type; the two connectors are provided for physical cabling convenience (left and right of the CPU cabinet).

	==External links==		==External links==

Jnc: fmt, models

2021-07-05T20:26:22Z

fmt, models

← Older revision		Revision as of 20:26, 5 July 2021
Line 19:		Line 19:
	\| price = US$200K (CPU), US$500K-1M (system)		\| price = US$200K (CPU), US$500K-1M (system)
	}}		}}

			[[Image:Sys37a.jpg\|thumb\|300px\|left\|KI10 at Tymshare]]

	The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[transistor-transistor logic\|TTL]] [[integrated circuit\|chip]]s, on [[FLIP CHIP]] cards.		The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[transistor-transistor logic\|TTL]] [[integrated circuit\|chip]]s, on [[FLIP CHIP]] cards.

	It was used in later[[DECsystem-10]] models, running [[TOPS-10]]. Via a series of kludges, it was also possible to run [[TENEX]] on the as-shipped hardware.		It was used in later [[DECsystem-10]] models, running [[TOPS-10]]. Via a series of kludges, it was also possible to run [[TENEX]] on the as-shipped hardware.

	It was the first PDP-10 model to provide [[paging]] in its as-shipped form, with 512-[[word]] pages. It was initially released in a single-[[central processing unit\|CPU]] version; a two-CPU version was released later.

	[[~~Image:Sys37a~~.~~jpg~~\|~~thumb\|left\|KI10 at Tymshare~~]]		It was the first PDP-10 model to provide [[paging]] in its as-shipped form, with 512-[[word]] pages. It was initially released in a single-[[central processing unit\|CPU]] version (DECsystem-1060 and -1070); a two-CPU version (DECsystem-1077) was released later.

	==External links==		==External links==

← Older revision		Revision as of 08:02, 9 June 2023
Line 22:		Line 22:
	[[Image:Sys37a.jpg\|thumb\|300px\|left\|KI10 at Tymshare]]		[[Image:Sys37a.jpg\|thumb\|300px\|left\|KI10 at Tymshare]]

	The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[transistor-transistor logic\|TTL]] [[integrated circuit\|chip]]s, on [[FLIP CHIP]] cards.		The '''KI10''' was the second generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of [[transistor-transistor logic\|TTL]] [[integrated circuit\|chip]]s, on small [[FLIP CHIP]] cards.

	It was the first PDP-10 model to provide [[paging]] in its as-shipped form, with 512-[[word]] pages. It was initially released in a single-[[central processing unit\|CPU]] version (DECsystem-1060 and -1070); a two-CPU version (DECsystem-1077) was released later.		It was the first PDP-10 model to provide [[paging]] in its as-shipped form, with 512-[[word]] pages. It was initially released in a single-[[central processing unit\|CPU]] version (DECsystem-1060 and -1070); a two-CPU version (DECsystem-1077) was released later.