KK11-A Cache Memory - Revision history

Jnc: Better cat

2022-10-12T00:36:08Z

Better cat

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	* [http://www.bitsavers.org/pdf/dec/pdp11/1134/MP00574_KK11-A_Aug78.pdf KK11-A Field Maintenance Print Set] (MP00574)		* [http://www.bitsavers.org/pdf/dec/pdp11/1134/MP00574_KK11-A_Aug78.pdf KK11-A Field Maintenance Print Set] (MP00574)

	[[Category: PDP-11 Processors]]		[[Category: PDP-11 UNIBUS Processors]]

Jnc: /* External links */ +FMPS, manual

2022-01-12T13:42:08Z

External links: +FMPS, manual

← Older revision		Revision as of 13:42, 12 January 2022
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	The '''KK11-A Cache Memory''' was an option for the [[KD11-EA CPU]], one which added a high-speed [[cache]] to the [[Central Processing Unit\|CPU]].		The '''KK11-A Cache Memory''' was an option for the [[KD11-EA CPU]], one which added a high-speed [[cache]] to the [[Central Processing Unit\|CPU]].

	Physically, it was a single [[DEC card form factor\|hex]] board, the M8268, interfaced to the CPU through an '[[over the back]]' connector. (This was because the [[PDP-11/34]] could be field-upgraded from a [[KD11-E CPU]], which did not support the cache, to a KD11-EA, which did - but the original [[DD11-P backplane]] was retained.)		Physically, it was a single [[DEC card form factor\|hex]] board, the '''M8268''', interfaced to the CPU through an '[[over the back]]' connector. (This was likely because the [[PDP-11/34]] could be field-upgraded from a [[KD11-E CPU]], which did not support the cache, to a KD11-EA, which did - but the original [[DD11-P backplane]] was retained.)

	==Technical detail==		==Technical detail==
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	Bit 0 refers to the most recent memory cycle. This field is the only one in the entire register set which is compatible with the -11/70.		Bit 0 refers to the most recent memory cycle. This field is the only one in the entire register set which is compatible with the -11/70.

	~~{{PDP~~-~~11}}~~		==External links==

			* [http://www.bitsavers.org/pdf/dec/pdp11/1134/EK-KK11A-UG-001_KK11-A_Cache_Memory_Users_Guide_Oct78.pdf KK11-A cache memory user's guide] (EK-KK11A-UG-001)
			* [http://www.bitsavers.org/pdf/dec/pdp11/1134/MP00574_KK11-A_Aug78.pdf KK11-A Field Maintenance Print Set] (MP00574)

	[[Category: PDP-11 Processors]]		[[Category: PDP-11 Processors]]

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2020-06-14T01:54:16Z

+image

← Older revision		Revision as of 01:54, 14 June 2020
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			[[Image:KK11-A.jpg\|250px\|right\|thumb\|KK11-A cache card]]

	The '''KK11-A Cache Memory''' was an option for the [[KD11-EA CPU]], one which added a high-speed [[cache]] to the [[Central Processing Unit\|CPU]].		The '''KK11-A Cache Memory''' was an option for the [[KD11-EA CPU]], one which added a high-speed [[cache]] to the [[Central Processing Unit\|CPU]].

	Physically, it was a single [[DEC card form factor\|hex]] board, the M8268, interfaced to the CPU through an 'over-the-back' connector. (This was because the [[PDP-11/34]] could be field-upgraded from a [[KD11-E CPU]], which did not support the cache, to a KD11-EA, which did - but the original backplane was retained.)		Physically, it was a single [[DEC card form factor\|hex]] board, the M8268, interfaced to the CPU through an '[[over the back]]' connector. (This was because the [[PDP-11/34]] could be field-upgraded from a [[KD11-E CPU]], which did not support the cache, to a KD11-EA, which did - but the original [[DD11-P backplane]] was retained.)

	==Technical detail==		==Technical detail==

	The KK11-A contained 1024 cache entries of high-speed [[Dynamic RAM\|DRAM]], in the form of 28 1024x1 DRAM chips. The cache was a direct-mapped cache (i.e. there was only one possible cache entry in which any given word of [[main memory]] could be found), with write-through, and a block size of one word.		The KK11-A contained 1024 cache entries of high-speed [[Dynamic RAM\|DRAM]], in the form of 28 1024x1 DRAM [[integrated circuit\|chips]]. The cache was a direct-mapped cache (i.e. there was only one possible cache entry in which any given word of [[main memory]] could be found), with write-through, and a block size of one [[word]].

	Each cache entry was 28 bits wide, containing two data bytes; a tag field for cache entries, 7 bits wide (covering [[UNIBUS]] address bits 17-11); 3 parity bits (one for the tag); and two valid bits (to allow the entire cache to be cleared by switching to a previously cleared set of valid bits).		Each cache entry was 28 bits wide, containing two data bytes; a tag field for cache entries, 7 bits wide (covering [[UNIBUS]] address bits 17-11); 3 [[parity]] bits (one for the tag); and two valid bits (to allow the entire cache to be cleared by switching to a previously cleared set of valid bits).

	==Installation==		==Installation==
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	\|Cache Hit Register \|\| CHR \|\| 777752		\|Cache Hit Register \|\| CHR \|\| 777752
	\|}		\|}


	In the register contents (below), read-write bits are shown in normal font, read-only in ''italics'', and write-only in '''bold'''.		In the register contents (below), read-write bits are shown in normal font, read-only in ''italics'', and write-only in '''bold'''.
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	{{16bit-bitout}}		{{16bit-bitout}}

	''Note: The manual says the 'CPU Abort' bit in the CME is bit 1, but the drawings show it as bit 0. Also, no indication is given as to whether these bits are read-only or not; likely they are.''		Note: The manual says the 'CPU Abort' bit in the CME is bit 1, but the drawings show it as bit 0. Also, no indication is given as to whether these bits are read-only or not; likely they are.

	===777746: Cache Control Register (CCR)===		===777746: Cache Control Register (CCR)===
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	{{16bit-bitout}}		{{16bit-bitout}}

	''Bit 0 refers to the most recent memory cycle. This field is the only one in the entire register set which is compatible with the -11/70.''		Bit 0 refers to the most recent memory cycle. This field is the only one in the entire register set which is compatible with the -11/70.

	{{PDP-11}}		{{PDP-11}}

	[[Category: PDP-11 Processors]]		[[Category: PDP-11 Processors]]

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2018-12-16T14:07:30Z

+cat

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	{{PDP-11}}		{{PDP-11}}

			[[Category: PDP-11 Processors]]

Jnc: Installation detail

2018-01-10T15:44:44Z

Installation detail

← Older revision		Revision as of 15:44, 10 January 2018
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	Physically, it was a single [[DEC card form factor\|hex]] board, the M8268, interfaced to the CPU through an 'over-the-back' connector. (This was because the [[PDP-11/34]] could be field-upgraded from a [[KD11-E CPU]], which did not support the cache, to a KD11-EA, which did - but the original backplane was retained.)		Physically, it was a single [[DEC card form factor\|hex]] board, the M8268, interfaced to the CPU through an 'over-the-back' connector. (This was because the [[PDP-11/34]] could be field-upgraded from a [[KD11-E CPU]], which did not support the cache, to a KD11-EA, which did - but the original backplane was retained.)

			==Technical detail==

	The KK11-A contained 1024 cache entries of high-speed [[Dynamic RAM\|DRAM]], in the form of 28 1024x1 DRAM chips. The cache was a direct-mapped cache (i.e. there was only one possible cache entry in which any given word of [[main memory]] could be found), with write-through, and a block size of one word.		The KK11-A contained 1024 cache entries of high-speed [[Dynamic RAM\|DRAM]], in the form of 28 1024x1 DRAM chips. The cache was a direct-mapped cache (i.e. there was only one possible cache entry in which any given word of [[main memory]] could be found), with write-through, and a block size of one word.

	Each cache entry was 28 bits wide, containing two data bytes; a tag field for cache entries, 7 bits wide (covering [[UNIBUS]] address bits 17-11); 3 parity bits (one for the tag); and two valid bits (to allow the entire cache to be cleared by switching to a previously cleared set of valid bits).		Each cache entry was 28 bits wide, containing two data bytes; a tag field for cache entries, 7 bits wide (covering [[UNIBUS]] address bits 17-11); 3 parity bits (one for the tag); and two valid bits (to allow the entire cache to be cleared by switching to a previously cleared set of valid bits).

			==Installation==

			This is mostly covered [[KD11-EA CPU#FP11-A/KK11-A installation\|here]], but there is one KK11-A specific detail: a backplane jumper must be present from pin C01E1 to pin B02A1 (the 'cache hit' line).

			A check is also required to make sure that the CPU's M8266 card is at the required ECO level - [[resistor]] 'R2' must be 1K ohms.

	==Registers==		==Registers==

Jnc: /* Registers */ Note -11/70 registers

2017-12-07T02:50:22Z

Registers: Note -11/70 registers

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	==Registers==		==Registers==

			The cache registers are at the same locations as some of the memory/cache registers in the [[PDP-11/70]], but they are generally incompatible with those in the /70, except as noted below.

	{\| border=1		{\| border=1
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	{{16bit-bitout}}		{{16bit-bitout}}

	''Bit 0 refers to the most recent memory cycle.''		''Bit 0 refers to the most recent memory cycle. This field is the only one in the entire register set which is compatible with the -11/70.''

	{{PDP-11}}		{{PDP-11}}

Jnc: Hit register flow direction

2017-12-06T22:27:39Z

Hit register flow direction

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	\| colspan=7 \| ''Tag Address'' \|\| colspan=3 \| Unused \|\| colspan=6 \| ''Hit Register''		\| colspan=7 \| ''Tag Address'' \|\| colspan=3 \| Unused \|\| colspan=6 \| ''Hit Register''
	{{16bit-bitout}}		{{16bit-bitout}}

			''Bit 0 refers to the most recent memory cycle.''

	{{PDP-11}}		{{PDP-11}}

Jnc: Add registers

2017-12-06T22:22:40Z

Add registers

← Older revision		Revision as of 22:22, 6 December 2017
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	Each cache entry was 28 bits wide, containing two data bytes; a tag field for cache entries, 7 bits wide (covering [[UNIBUS]] address bits 17-11); 3 parity bits (one for the tag); and two valid bits (to allow the entire cache to be cleared by switching to a previously cleared set of valid bits).		Each cache entry was 28 bits wide, containing two data bytes; a tag field for cache entries, 7 bits wide (covering [[UNIBUS]] address bits 17-11); 3 parity bits (one for the tag); and two valid bits (to allow the entire cache to be cleared by switching to a previously cleared set of valid bits).

			==Registers==

			{\| border=1
			! Register !! Abbreviation !! Address
			\|-
			\|Cache Memory Error Register \|\| CME \|\| 777744
			\|-
			\|Cache Control Register \|\| CCR \|\| 777746
			\|-
			\|Cache Maintenance Register \|\| CMR \|\| 777750
			\|-
			\|Cache Hit Register \|\| CHR \|\| 777752
			\|}


			In the register contents (below), read-write bits are shown in normal font, read-only in ''italics'', and write-only in '''bold'''.

			===777744: Cache Memory Error Register (CME)===
			{{16bit-header}}
			\| colspan=8 \| Unused \|\| ''High Byte Parity'' \|\| ''Low Byte Parity'' \|\| ''Tag Parity'' \|\| colspan=4 \| Unused \|\| ''CPU Abort''
			{{16bit-bitout}}

			''Note: The manual says the 'CPU Abort' bit in the CME is bit 1, but the drawings show it as bit 0. Also, no indication is given as to whether these bits are read-only or not; likely they are.''

			===777746: Cache Control Register (CCR)===
			{{16bit-header}}
			\| colspan=2 \| Unused \|\| ''Valid Store In Use'' \|\| ''Valid Clear In Progress'' \|\| Unused \|\| Write Wrong Parity Tag \|\| Unconditional Cache Bypass \|\| '''Flush Cache''' \|\| Parity Error Abort \|\| Write Wrong Parity Data \|\| colspan=2 \| Unused \|\| Force Miss High \|\| Force Miss Low \|\| Unused \|\| Disable Cache Parity Interrupt
			{{16bit-bitout}}

			===777750: Cache Maintenance Register (CMR)===
			{{16bit-header}}
			\| colspan=15 \| Unused \|\| Write Tag All Ones
			{{16bit-bitout}}

			===777752: Cache Hit Register (CHR)===
			{{16bit-header}}
			\| colspan=7 \| ''Tag Address'' \|\| colspan=3 \| Unused \|\| colspan=6 \| ''Hit Register''
			{{16bit-bitout}}

	{{PDP-11}}		{{PDP-11}}

Jnc: A good start, need to add registers

2017-12-06T16:16:33Z

A good start, need to add registers

New page

The '''KK11-A Cache Memory''' was an option for the [[KD11-EA CPU]], one which added a high-speed [[cache]] to the [[Central Processing Unit|CPU]].

Physically, it was a single [[DEC card form factor|hex]] board, the M8268, interfaced to the CPU through an 'over-the-back' connector. (This was because the [[PDP-11/34]] could be field-upgraded from a [[KD11-E CPU]], which did not support the cache, to a KD11-EA, which did - but the original backplane was retained.)

The KK11-A contained 1024 cache entries of high-speed [[Dynamic RAM|DRAM]], in the form of 28 1024x1 DRAM chips. The cache was a direct-mapped cache (i.e. there was only one possible cache entry in which any given word of [[main memory]] could be found), with write-through, and a block size of one word.

Each cache entry was 28 bits wide, containing two data bytes; a tag field for cache entries, 7 bits wide (covering [[UNIBUS]] address bits 17-11); 3 parity bits (one for the tag); and two valid bits (to allow the entire cache to be cleared by switching to a previously cleared set of valid bits).

{{PDP-11}}