KL10 - Revision history

Larsbrinkhoff: This page was archived, and supposedly has same content.

2024-11-11T15:01:49Z

This page was archived, and supposedly has same content.

Jnc: Fix Super Foonly link

2024-11-10T02:13:55Z

Fix Super Foonly link

Jnc: S/X Bus was usually called the 'internal' memory bus

2024-04-02T11:06:38Z

S/X Bus was usually called the 'internal' memory bus

Jnc: Clarify MCA20 functionality

2023-11-14T16:15:38Z

Clarify MCA20 functionality

Jnc: /* External Links */ KL10 Project Technology Goals

2023-11-12T22:55:02Z

‎External Links: KL10 Project Technology Goals

Jnc: The initial cache was the MCA20

2023-11-12T21:19:14Z

The initial cache was the MCA20

Jnc: /* Versions */ No such thing as a 'Model E'

2023-11-12T20:28:27Z

‎Versions: No such thing as a 'Model E'

Jnc: Clock speeds in Model A and Model B

2023-11-12T13:59:48Z

Clock speeds in Model A and Model B

Larsbrinkhoff: However, cache size isn't a Model A/B thing.

2023-11-12T13:13:51Z

However, cache size isn't a Model A/B thing.

Larsbrinkhoff: The rest of the infobox uses Model A/B in the "informal internal" sense where there is no Model E. 23-bit virtual address would be KL10-E (and D & R), but that's a "Model B".

2023-11-12T12:48:30Z

The rest of the infobox uses Model A/B in the "informal internal" sense where there is no Model E. 23-bit virtual address would be KL10-E (and D & R), but that's a "Model B".

@@ Line 123: / Line 123: @@
 * [https://www.cca.org/tech/rcs/pdp-11-40/ PDP-11/40] - good images of a KL10 front end
 * [http://www.brouhaha.com/~eric/retrocomputing/pdp-10/kl10d_modules.html KL-10D Module Utilization]
-<!-- * [http://ftp.inwap.com/pdp10/usenet/kl KL] - some interesting discussion of KL10 details not in Internet archive -->
+* [http://web.archive.org/web/20150919094256/http://www.inwap.com/pdp10/usenet/kl KL] - some interesting discussion of KL10 details
 * [http://infolab.stanford.edu/pub/voy/museum/pictures/AIlab/SailFarewell.html SAIL Farewell] - a good thumbnail history
 * [https://github.com/PDP-10/its/tree/master/src/ucode KL10 ITS microcode]
 [[Category: PDP-10 Processors]]

@@ Line 23: / Line 23: @@
 }}
-The '''KL10''' was the third generation of [[PDP-10]] processors. It was built out of [[Emitter-coupled logic|ECL]], on [[DEC card form factor|hex]] cards. It was the first [[microcode|micro-programmed]] PDP-10 processor; the design was inspired by Stanford's [[Superfoonly]].
+The '''KL10''' was the third generation of [[PDP-10]] processors. It was built out of [[Emitter-coupled logic|ECL]], on [[DEC card form factor|hex]] cards. It was the first [[microcode|micro-programmed]] PDP-10 processor; the design was inspired by Stanford's [[Super Foonly]].
 The [[Central Processing Unit|CPU]] had two main units, the 'E Box' ('Execution') and the 'M Box' ('Memory'). It provided three types of [[bus]]ses to the rest of the components of the system; the 'E Bus', from the E Box; and the 'S Bus' ('Storage'), and later the 'C Bus' ('[[Channel]]'), from the M Box. The S Bus (usually called the 'internal' memory bus) was for the attachment of [[main memory]] units, while the C Bus allowed [[Direct Memory Access|DMA]] accesss to main memory.
@@ Line 123: / Line 123: @@
 * [https://www.cca.org/tech/rcs/pdp-11-40/ PDP-11/40] - good images of a KL10 front end
 * [http://www.brouhaha.com/~eric/retrocomputing/pdp-10/kl10d_modules.html KL-10D Module Utilization]
-* [http://ftp.inwap.com/pdp10/usenet/kl KL] - some interesting discussion of KL10 details
+<!-- * [http://ftp.inwap.com/pdp10/usenet/kl KL] - some interesting discussion of KL10 details not in Internet archive -->
 * [http://infolab.stanford.edu/pub/voy/museum/pictures/AIlab/SailFarewell.html SAIL Farewell] - a good thumbnail history
 * [https://github.com/PDP-10/its/tree/master/src/ucode KL10 ITS microcode]
 [[Category: PDP-10 Processors]]

@@ Line 25: / Line 25: @@
 The '''KL10''' was the third generation of [[PDP-10]] processors. It was built out of [[Emitter-coupled logic|ECL]], on [[DEC card form factor|hex]] cards. It was the first [[microcode|micro-programmed]] PDP-10 processor; the design was inspired by Stanford's [[Superfoonly]].
-The [[Central Processing Unit|CPU]] had two main units, the 'E Box' ('Execution') and the 'M Box' ('Memory'). It provided three types of [[bus]]ses to the rest of the components of the system; the 'E Bus', from the E Box; and the 'S Bus' ('Storage'), and later the 'C Bus' ('[[Channel]]'), from the M Box. The S Bus was for the attachment of [[main memory]] units, while the C Bus allowed [[Direct Memory Access|DMA]] accesss to main memory.
+The [[Central Processing Unit|CPU]] had two main units, the 'E Box' ('Execution') and the 'M Box' ('Memory'). It provided three types of [[bus]]ses to the rest of the components of the system; the 'E Bus', from the E Box; and the 'S Bus' ('Storage'), and later the 'C Bus' ('[[Channel]]'), from the M Box. The S Bus (usually called the 'internal' memory bus) was for the attachment of [[main memory]] units, while the C Bus allowed [[Direct Memory Access|DMA]] accesss to main memory.
 (The S Bus was later modififed to a version called the 'X Bus', which was functionally the same as the S Bus, but used [[transistor-transistor logic|TTL]] [[signal]] [[voltage]]s, instead of the [[emitter-coupled logic|ECL]] levels of the S Bus.)
@@ Line 33: / Line 33: @@
 A main memory [[cache]] for [[instruction]] and [[operand]] [[fetch]]es, the [[MCA20 Cache]] - standard in some models, and optional in others - was available. Later in the KL10's life, the improved [[MCA25 KL Cache/Paging Upgrade]], which increased both the size of both the main memory cache, and the [[virtual memory|paging]] cache, as well as improved the functionality of the latter, could be added/substituted for the MCA20.
-A [[DMA20 Memory Bus Adapter]] could be attached to the S Bus, to provide up to 4 (in parallel, to increase memory bandwidth, as well as maximizing [[memory interleaving]]) [[KI10]]-compatible [[PDP-10 Memory Bus|external memory busses]] (called the K Bus in the KL10). Similarly, an [[DIA20 In/Out Bus Controller]] could be attached to the E Bus, to provide a [[PDP-10 I/O Bus]] (called the I Bus in the KL10).
+A [[DMA20 Memory Bus Adapter]] could be attached to the S Bus, to provide up to 4 (in parallel, to increase memory bandwidth, as well as maximizing [[memory interleaving]]) [[KI10]]-compatible [[PDP-10 Memory Bus|external memory busses]] (called the 'K Bus' in the KL10). Similarly, an [[DIA20 In/Out Bus Controller]] could be attached to the E Bus, to provide a [[PDP-10 I/O Bus]] (called the I Bus in the KL10).
 The KL10 was used in the [[DECsystem-10]] models 108x and 109x systems (initially with an external memory bus and an I/O bus, as a 'drop-in' processor replacement for a KI10), and in the high-end 20xx systems of the [[DECSYSTEM-20]] line (with an internal memory bus).
@@ Line 48: / Line 48: @@
 * [[CI20 Computer Interconnect]] - interface to the [[Computer Interconnect|CI]] high-speed link
-If either the NIA2O or CI20 in installed, since they use some of the backplane slots for the RH20's, only 4 RH20's may be installed if either is installed. They also connect to the EBUS and CBUS.
+If either the NIA2O or CI20 in installed, since they use some of the [[backplane]] slots for the RH20's, only 4 RH20's may be installed if either is installed. They also connect to the EBUS and CBUS.
 All low-speed devices were generally attached to the [[UNIBUS]] of one of the PDP-11 front ends (which could also be attached via a [[DL10 PDP-11 Data Link|DL10]]); although the I Bus provided by a DIA20 was also an option.
@@ Line 56: / Line 56: @@
 There were two main packaging families: those used for the DECsystem-10, which used tall, medium-width cabinets like those of the KA10 and KI10, in the same turquoise blue as the latter; and the DECSYSTEM-20, which were shorter and wider and painted cream and orange.
-The CPU, front end, and I/O controllers were accommodated in a set of three racks (or four, for some DECSYSTEM-20s); one to hold the CPU, one for the front-end, and one for all the I/O. The E Box and the M Box were both on the main [[backplane]], in the CPU cabinet. The DMA20, DIA20, DTE20s and RH20s were all accommodated on backplanes in the second, I/O, cabinet; the first two were on a single backplane, and the latter two on another.
+The CPU, front end, and I/O controllers were accommodated in a set of three racks (or four, for some DECSYSTEM-20s); one to hold the CPU, one for the front-end, and one for all the I/O. The E Box and the M Box were both on the main backplane, in the CPU cabinet. The DMA20, DIA20, DTE20s and RH20s were all accommodated on backplanes in the second, I/O, cabinet; the first two were on a single backplane, and the latter two on another.
 ==Versions==
@@ Line 100: / Line 100: @@
 Note that the early KL10-A only supported a single DTE20, and no RH20s, and it was the later KL10-B and up (the first two also with the Model A CPU), which supported up to 4 DTE20s and up to 8 RH20s. This is because the I/O backplanes in the second bay of the CPU differed in the KL10-B and up, to support the larger I/O configuration. (The DTE20 backplane differed between the two.) The KL10-A was intended to replace KA10 and KI10 processors, hence the lack of support for RH20s, etc.
-One significant division between KL-based ''systems'' is between those with an external memory bus, and those with an internal memory bus (the native S Bus).
+One significant division between KL-based ''systems'' is between those with an external memory bus (K bus), and those with an internal memory bus (the native S/X Bus).
 The DEC numeric model numbers - a fourth namespace - are even more confused, since a 1090 could be either a "KL10-B(PA) or KL10-D(PV)"; similarly, the 2040 and 2050 could be a "KL10-C(PA) or KL10-E(PV)".
@@ Line 108: / Line 108: @@
 There was a single KL10 [[Incompatible Timesharing System|ITS]] machine, MIT-MC, a very early Model A. It was later renamed to MX after a [[KS10]] took the 'MC' identity, and was finally shut down in 1988; it is now in storage at the [[Living Computer Museum]].
-The [[Stanford Artificial Intelligence Laboratory|SAIL]] (or SU-AI) [[timesharing]] system — [[WAITS]] — main computer was a KL10 from 1976 to [http://infolab.stanford.edu/pub/voy/museum/pictures/AIlab/SailFarewell.html 1991].  In 1983, it was upgraded from a model A to a model B CPU.  Near the end, failing isolation in the [[backplane]] was fixed by inserting toothpicks.
+The [[Stanford Artificial Intelligence Laboratory|SAIL]] (or SU-AI) [[time-sharing]] system — [[WAITS]] — main computer was a KL10 from 1976 to 1991.  In 1983, it was upgraded from a model A to a model B CPU.  Near the end, failing insulation in the backplane was fixed by inserting toothpicks.
 ==External Links==
@@ Line 121: / Line 121: @@
 * [http://www.shiresoft.com/pdp-11/kl-10/ KL-10]
 ** [http://www.shiresoft.com/pdp-11/kl-10/io-connectors.jpg KL10 I/O connectors] - Good image of bus connectors: on the bottom, MASSBUS connectors on the left; memory and I/O bus QuickLatch connectors on the right
 * [http://www.brouhaha.com/~eric/retrocomputing/pdp-10/kl10d_modules.html KL-10D Module Utilization]
 * [http://ftp.inwap.com/pdp10/usenet/kl KL] - some interesting discussion of KL10 details
-* [https://github.com/PDP-10/its/tree/master/src/ucode ITS microcode]
+* [http://infolab.stanford.edu/pub/voy/museum/pictures/AIlab/SailFarewell.html SAIL Farewell] - a good thumbnail history
 [[Category: PDP-10 Processors]]

@@ Line 31: / Line 31: @@
 A KL10 could support up to 4 [[DTE20 Ten-Eleven Interface‎‎]]s; they allowed connection of a [[PDP-11]] [[front end]]. At least one PDP-11, the 'master', was ''required''; it could [[bootstrap]] the KL10, including loading the [[microcode]].
-A main memory [[cache]], the MCA20 - standard in some models, and optional in others - was available. Later in the KL10's life, the improved [[MCA25 KL Cache/Paging Upgrade]], which increased both the size of both the main memory cache, and the [[virtual memory|paging]] cache, as well as improved the functionality of the latter, could be added/substituted for the MCA20.
+A main memory [[cache]] for [[instruction]] and [[operand]] [[fetch]]es, the [[MCA20 Cache]] - standard in some models, and optional in others - was available. Later in the KL10's life, the improved [[MCA25 KL Cache/Paging Upgrade]], which increased both the size of both the main memory cache, and the [[virtual memory|paging]] cache, as well as improved the functionality of the latter, could be added/substituted for the MCA20.
 A [[DMA20 Memory Bus Adapter]] could be attached to the S Bus, to provide up to 4 (in parallel, to increase memory bandwidth, as well as maximizing [[memory interleaving]]) [[KI10]]-compatible [[PDP-10 Memory Bus|external memory busses]] (called the K Bus in the KL10). Similarly, an [[DIA20 In/Out Bus Controller]] could be attached to the E Bus, to provide a [[PDP-10 I/O Bus]] (called the I Bus in the KL10).
@@ Line 74: / Line 74: @@
 The KL10-PV supported the 'Extended' PDP-10 [[architecture]], with support for multiple 'sections' (256K-[[word]] [[address space]]s), available to both the [[kernel]] and the [[user]] (although apparently only [[TOPS-20]] supported the latter). The earlier machines could be field upgraded to a -PV, but it apparently needed a modified/new backplane.
-Substitution/addition of the later MCA25 cache produced the KL10-PW. It too required backplane modifications; the resulting machine was termed the 'Model C' by some.
+Substitution/addition of the later MCA25 cache produced the KL10-PW; the resulting machine was named the 'Model C' by some.
 Many of the 'models' (e.g. 'KL10-C' and 'KL10-D') appear to be names for particular configurations (with various options, such as the DMA20 and DIA20); here is a DEC table which (hopefully authoritatively) defines them:

@@ Line 116: / Line 116: @@
 ** [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-1080U-SD-003_1080_1090_SysDescr_Jan77.pdf decsystem-1080/1090 System Description] (EK-1080U-SD-003) - good medium-level description of the functionality of the KL10 CPU and its peripherals
 ** [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-108OU-PD-002_KL10-Based_Physical_Description_Mar77.pdf KL10-Based Physical Description] (EK-108OU-PD-002) - contains KL10 board configuration, pp. 3-29
 * [https://dodlithr.blogspot.com/2014/04/digitals-decsystem-20-part-5-cpu-kl10.html Digital's DECSYSTEM-20 - Part 5 - CPU (KL10)]
 * [http://corestore.org/DEC2065.htm Corestore collection: DECSYSTEM 2065 KL10-RH] - Good images, has two MG20 memory units

@@ Line 30: / Line 30: @@
 A KL10 could support up to 4 [[DTE20 Ten-Eleven Interface‎‎]]s; they allowed connection of a [[PDP-11]] [[front end]]. At least one PDP-11, the 'master', was ''required''; it could [[bootstrap]] the KL10, including loading the [[microcode]].
 A [[DMA20 Memory Bus Adapter]] could be attached to the S Bus, to provide up to 4 (in parallel, to increase memory bandwidth, as well as maximizing [[memory interleaving]]) [[KI10]]-compatible [[PDP-10 Memory Bus|external memory busses]] (called the K Bus in the KL10). Similarly, an [[DIA20 In/Out Bus Controller]] could be attached to the E Bus, to provide a [[PDP-10 I/O Bus]] (called the I Bus in the KL10).
@@ Line 72: / Line 74: @@
 The KL10-PV supported the 'Extended' PDP-10 [[architecture]], with support for multiple 'sections' (256K-[[word]] [[address space]]s), available to both the [[kernel]] and the [[user]] (although apparently only [[TOPS-20]] supported the latter). The earlier machines could be field upgraded to a -PV, but it apparently needed a modified/new backplane.
-Substitution/addition of the later [[MCA25 KL Cache/Paging Upgrade]], which increased both the size of both the main memory [[cache]], and the [[Virtual memory|paging]] cache, as well as improved the functionality of the latter, produced the -PW. It too required backplane modifications; the resulting machine was termed the 'Model C' by some.
+Substitution/addition of the later MCA25 cache produced the KL10-PW. It too required backplane modifications; the resulting machine was termed the 'Model C' by some.
 Many of the 'models' (e.g. 'KL10-C' and 'KL10-D') appear to be names for particular configurations (with various options, such as the DMA20 and DIA20); here is a DEC table which (hopefully authoritatively) defines them:
 {| class="wikitable"
-! Model !! PV !! Cache !! Int Chans !! Max DTEs !!Max RH20s !! DIA !! DMA
+! Model !! PV !! Cache !! Int Chans !! Max DTEs !! Max RH20s !! DIA !! DMA
 |-
 | KL10-A || No || Yes || No || 1 || 0 || Yes || Yes

@@ Line 94: / Line 94: @@
 (*: Maximum 4 RH20s if a CI20 or NIA20 is installed, as those use the slots for RH4-7 in the RH20 backplane.)
-The 'KL10-R' appears to be a Model E in a new cabinet design, one compliant with newer FCC [[interference|RFI]] emissions standards; but it may also refer to systems with the MCA25.
+The 'KL10-R' appears to be a KL10-E in a new cabinet design, one compliant with newer FCC [[interference|RFI]] emissions standards; but it may also refer to systems with the MCA25.
 Note that the early KL10-A only supported a single DTE20, and no RH20s, and it was the later KL10-B and up (the first two also with the Model A CPU), which supported up to 4 DTE20s and up to 8 RH20s. This is because the I/O backplanes in the second bay of the CPU differed in the KL10-B and up, to support the larger I/O configuration. (The DTE20 backplane differed between the two.) The KL10-A was intended to replace KA10 and KI10 processors, hence the lack of support for RH20s, etc.

@@ Line 13: / Line 13: @@
 | uword width = 75 (Model A)<br>76 (Model B)
 | ucode length = 1280 (Model A)<br>2K (Model B)
-| clock speed = 500 nsec
+| clock speed = 50 MHz (Model A)<br>58 MHz (Model B)
 | cache size = 2K words (KL10-PA and PV)<br>4K words (KL10-PW)
 | memory speed = 1.0 μsec (initial [[core memory]]), 500 nsec (later [[Metal Oxide Semiconductor|MOS]] [[main memory]])

@@ Line 8: / Line 8: @@
 | word size = 36 bits
 | physical address = 22 bits
-| virtual address = 18 bits (Model A and B)<br>23 bits (Model E)
+| virtual address = 18 bits (Model A)<br>23 bits (Model B)
 | logic type = [[emitter-coupled logic|ECL]] [[IC]]s
 | design type =  clocked synchronous, [[microcode]]d