KS10 - Revision history

Jnc: /* External links */ +one from Paul Allen's collection at the LCM

2025-04-24T17:08:14Z

‎External links: +one from Paul Allen's collection at the LCM

Larsbrinkhoff: /* Software */ Also TYMCOM-XX.

2023-07-14T17:48:25Z

‎Software: Also TYMCOM-XX.

Jnc: /* Software */ Ran TOPS-10, TOPS-20 and ITS

2023-07-14T11:48:42Z

‎Software: Ran TOPS-10, TOPS-20 and ITS

Jnc: /* Internal details */ cache and registers share a register file

2022-11-05T02:32:04Z

‎Internal details: cache and registers share a register file

Jnc: add image

2022-11-03T12:48:11Z

add image

Jnc: minor copyedits

2022-11-03T12:10:04Z

minor copyedits

Jnc: Bus details

2022-11-02T16:25:44Z

Bus details

Jnc: give overview of internal organization

2022-11-02T05:59:09Z

give overview of internal organization

Jnc: +Category: DEC Documentation Errors

2022-10-25T13:36:57Z

+Category: DEC Documentation Errors

Jnc: /* External links */ Make URL work

2022-04-11T05:57:58Z

‎External links: Make URL work

@@ Line 129: / Line 129: @@
 * [http://www.corestore.org/DEC20.htm DECSYSTEM 2020] - good images of the internals
 * [https://sites.google.com/site/mthompsonorg/Home/pdp-10/ks10 DECSYSTEM-2020 KS10, S/N 4224] - also has images of the internals
 [[Category: PDP-10 Processors]]
 [[Category: UNIBUS Processors]]
 [[Category: DEC Documentation Errors]]

@@ Line 115: / Line 115: @@
 ==Software==
-DEC supported both [[TOPS-10]] and [[TOPS-20]] on the KS10. Later, the [[Incompatible Timesharing System]] was made to run on it, and [[Massachusetts Institute of Technology|MIT]] had several.
+DEC supported both [[TOPS-10]] and [[TOPS-20]] on the KS10. Later, the [[Incompatible Timesharing System]] was made to run on it, and [[Massachusetts Institute of Technology|MIT]] had several.  [[Tymshare]] ran a version of their operating system called [[TYMCOM-X|TYMCOM-XX]].
 ==External links==

@@ Line 112: / Line 112: @@
 * The "M8014" in the UNIBUS 'A' In slot must be an M9014 (UNIBUS to 3 [[flat cable]]s; the M8014 is an [[RL11 disk controller|RLV11]] board).
 ==External links==
-* [http://www.bitsavers.org/pdf/dec/pdp10/KS10/ KS1] - BitSavers KS10 directory
+* [http://www.bitsavers.org/pdf/dec/pdp10/KS10/ KS10] - BitSavers KS10 directory
 ** [http://www.bitsavers.org/pdf/dec/pdp10/KS10/EK-OKS10-TM-002_tech_Sep79.pdf KS10-Based DECSYSTEM-2020 Technical Manual] (EK-0KS10-TM-002)
-* [https://github.com/PDP-10/its/tree/master/src/kshack ITS KS10 support] - includes microcode source
+* [https://github.com/PDP-10/its-vault/tree/master/files/kshack ITS KS10 support] - includes microcode source
 * [http://www.techtravels.org/KS10FPGA/ks10_manual_rd40.pdf KS10 FPGA Processor Manual] - reimplementation of the KS10 in an [[FPGA]]
 * [http://www.corestore.org/DEC20.htm DECSYSTEM 2020] - good images of the internals

@@ Line 39: / Line 39: @@
 ==Internal details==
-The I/O [[instruction]]s were completely different from the other PDP-10 models, in part because the machine only had UNIBUSes; external I/O instructions had to specify the UNIBUS address, and also which UNIBUS adapter is being used.
+The I/O [[instruction]]s were completely different from the other PDP-10 models, in part because the machine only had UNIBUSes; external I/O instructions had to specify the UNIBUS address, and also which UNIBUS adapter is being used. Separate [[page table]]s mapped the UNIBUS [[address space]] into the KS10's main memory for [[Direct Memory Access|DMA]] operations.
-The CPU has a 512-entry memory [[cache]]; 1-way set associative on individual words. It also has 8 different sets of [[register]]s, to speed up interrupt handling. (Set 7 is reserved for use by the microcode.) Separate [[page table]]s mapped the UNIBUS [[address space]] into the KS10's main memory for [[Direct Memory Access|DMA]] operations.
+The CPU has a 512-entry memory [[cache]]; 1-way set associative on individual words. It also has 8 different sets of [[register]]s, to speed up interrupt handling. (Set 7 is reserved for use by the microcode.) The cache and register sets are all stored in the same 300 nsec [[register file]].
 The UNIBUS which is used for the disks was run in [[UNIBUS parity#18-bit width|18-bit mode]] (the two [[parity]] lines on that UNIBUS were recycled into two extra data lines). That UNIBUS had only an RH11-C, mounted in the main CPU rack (although apparently on its own backplane) to drive the MASSBUS to the disks. (Only MASSBUS disks were supported on that RH11-C, apparently both for performance reasons, and since 18-bit data storage was needed).

@@ Line 1: / Line 1: @@
 {{Infobox Machine
 | name = KS10
 | manufacturer = [[Digital Equipment Corporation]]
 | architecture = [[PDP-10]]
@@ Line 117: / Line 119: @@
 * [https://github.com/PDP-10/its/tree/master/src/kshack ITS KS10 support] - includes microcode source
 * [http://www.techtravels.org/KS10FPGA/ks10_manual_rd40.pdf KS10 FPGA Processor Manual] - reimplementation of the KS10 in an [[FPGA]]
-* [https://sites.google.com/site/mthompsonorg/Home/pdp-10/ks10 DECSYSTEM-2020 KS10, S/N 4224] - has images of the internals
+* [http://www.corestore.org/DEC20.htm DECSYSTEM 2020] - good images of the internals
 [[Category: PDP-10 Processors]]
 [[Category: UNIBUS Processors]]
 [[Category: DEC Documentation Errors]]

@@ Line 27: / Line 27: @@
 The KS10 is organized around a [[synchronous]] [[bus]] (carried only on the main [[backplane]]), to which are attached the [[microcode]]d [[Central Processing Unit|CPU]], the [[main memory]] controller, and two or three [[UNIBUS]] adapters (which are used to perform all [[input/output|I/O]] in the system. [[Parity]] is used throughout for error detection.
-These two types of bus, along with [[MASSBUS]]es provided by [[RH11 MASSBUS controller|RH11-C]]'s on the UNIBUSes, are the only buses in the KS10; it supports neither the [[PDP-10 Memory Bus]] nor the [[PDP-10 I/O Bus]]. [[Address]]es and data share one set of multiplexed [[conductor]]s; the address is transferred on one cycle, and the associated data on a following cycle.
+These two types of bus, along with [[MASSBUS]]es provided by [[RH11 MASSBUS controller|RH11-C]]'s on the UNIBUSes, are the only buses in the KS10; it supports neither the [[PDP-10 Memory Bus]] nor the [[PDP-10 I/O Bus]]. [[Address]]es and data share one set of multiplexed [[conductor]]s on the KS10 internal bus; the address is transferred on one cycle, and the associated data on a following cycle.
-The KS10's internal bus also supports [[interrupt]]s from the UNIBUS adapters, as well as [[diagnostic]] access from the mandatory 'console' subsystem, which is also interfaced to the KS10 bus. It contains an [[Intel 8080|8080]] [[microprocessor]] controlled by a [[read-only memory|PROM]], and is used to [[bootstrap]] the system, load the CPU's wholly writeable microcode, etc.
+That bus also supports [[interrupt]]s from the UNIBUS adapters, as well as [[diagnostic]] access from the mandatory 'console' subsystem, which is interfaced to the KS10 bus. It contains an [[Intel 8080|8080]] [[microprocessor]] controlled by a [[read-only memory|PROM]], and is used to [[bootstrap]] the system, load the CPU's wholly writeable microcode, etc.
 The memory is specific to the KS10; it used 7 extra bits per word to hold [[error-correcting code|ECC]] data, for double-bit error detection and single-bit correction. It is all connected to the memory controller through a private bus, which is also present only on the main backplane.
@@ Line 39: / Line 39: @@
 The I/O [[instruction]]s were completely different from the other PDP-10 models, in part because the machine only had UNIBUSes; external I/O instructions had to specify the UNIBUS address, and also which UNIBUS adapter is being used.
-The CPU has a 512-entry memory [[cache]]; 1-way set associative on words. It also has 8 different sets of [[register]]s, to speed up interrupt handling. (Set 7 is reserved for use by the microcode.) Separate [[page table]]s mapped the UNIBUS [[address space]] into the KS10's main memory for [[Direct Memory Access|DMA]] operations.
+The CPU has a 512-entry memory [[cache]]; 1-way set associative on individual words. It also has 8 different sets of [[register]]s, to speed up interrupt handling. (Set 7 is reserved for use by the microcode.) Separate [[page table]]s mapped the UNIBUS [[address space]] into the KS10's main memory for [[Direct Memory Access|DMA]] operations.
 The UNIBUS which is used for the disks was run in [[UNIBUS parity#18-bit width|18-bit mode]] (the two [[parity]] lines on that UNIBUS were recycled into two extra data lines). That UNIBUS had only an RH11-C, mounted in the main CPU rack (although apparently on its own backplane) to drive the MASSBUS to the disks. (Only MASSBUS disks were supported on that RH11-C, apparently both for performance reasons, and since 18-bit data storage was needed).

@@ Line 8: / Line 8: @@
 | physical address = 19 bits (some had 20)
 | virtual address = 18 bits
-| logic type = [[LS TTL]] [[IC]]s
+| logic type = [[LS TTL]] [[integrated circuit|IC]]s
-| design type =  clocked synchronous [[microcode]]d
+| design type = clocked synchronous [[microcode]]d
 | uword width = 96
 | ucode length = 2K
@@ Line 16: / Line 16: @@
 | cache speed = 300 nsec
 | memory speed = 0.9 μsec
-| memory mgmt = [[paging]], 512-word pages
+| memory mgmt = [[virtual memory|paging]], 512-word pages
 | operating system = [[TOPS-10]], [[TOPS-20]], [[Incompatible Timesharing System|ITS]], [[TYMCOM-XX]]
 | predecessor = [[KL10]]
@@ Line 23: / Line 23: @@
 }}
-The '''KS10''' was the fourth and last generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was intended as a small, low-cost entry model, not as a replacement for the earlier [[KL10]] [[mainframe]].  A few documents refer to it as the '''SM10''', maybe "small 10".
+The '''KS10''' was the fourth and last generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture) from [[Digital Equipment Corporation|DEC]]. It was intended as a small, low-cost entry model, not as a replacement for the earlier [[KL10]] [[mainframe]].  A few documents refer to it as the '''SM10''', maybe "small 10".
-The KS10 is organized around a [[synchronous]] [[bus]], to which are attached the [[microcode]]d [[Central Processing Unit|CPU]], the [[main memory]] controller, and two or three [[UNIBUS]] adapters (which are used to perform all [[input/output|I/O]] in the system.
+The KS10 is organized around a [[synchronous]] [[bus]] (carried only on the main [[backplane]]), to which are attached the [[microcode]]d [[Central Processing Unit|CPU]], the [[main memory]] controller, and two or three [[UNIBUS]] adapters (which are used to perform all [[input/output|I/O]] in the system. [[Parity]] is used throughout for error detection.
-A 'console' subsystem is also interfaced to the KS10's internal bus; it contains an [[Intel 8080|8080]] [[microprocessor]], and is used to load the microcode, [[bootstrap]] the system, etc.
+These two types of bus, along with [[MASSBUS]]es provided by [[RH11 MASSBUS controller|RH11-C]]'s on the UNIBUSes, are the only buses in the KS10; it supports neither the [[PDP-10 Memory Bus]] nor the [[PDP-10 I/O Bus]]. [[Address]]es and data share one set of multiplexed [[conductor]]s; the address is transferred on one cycle, and the associated data on a following cycle.
-The memory is specific to the KS10; it used 7 extra bits per word to hold [[error-correcting code|ECC]] data, for error detection and correction. All KS10's contain at least two UNIBUS adapters (a third is optional); one was for the [[disk]]s only, the other for all other [[peripheral]]s ([[magnetic tape]], [[asynchronous serial line]]s, etc).
+The KS10's internal bus also supports [[interrupt]]s from the UNIBUS adapters, as well as [[diagnostic]] access from the mandatory 'console' subsystem, which is also interfaced to the KS10 bus. It contains an [[Intel 8080|8080]] [[microprocessor]] controlled by a [[read-only memory|PROM]], and is used to [[bootstrap]] the system, load the CPU's wholly writeable microcode, etc.
 ==Internal details==
-different sets of CPU [[register]]s were provided, to speed up [[interrupt]] handling. Separate [[page table]]s mapped the UNIBUS [[address space]] into the KS10's main memory for [[Direct Memory Access|DMA]] operations.
+The I/O [[instruction]]s were completely different from the other PDP-10 models, in part because the machine only had UNIBUSes; external I/O instructions had to specify the UNIBUS address, and also which UNIBUS adapter is being used.
-The UNIBUS which is used for the disks was run in [[UNIBUS parity#18-bit width|18-bit mode]] (the two [[parity]] lines on that UNIBUS were recycled into two extra data lines). That UNIBUS had only an [[RH11 MASSBUS controller|RH11-C]], mounted in the main CPU rack (although apparently on its own [[backplane]]) to drive the [[MASSBUS]] to the disks. (Only MASSBUS disks were supported on that RH11, apparently both for performance reasons, and since 18-bit data storage was needed).
+The UNIBUS which is used for the disks was run in [[UNIBUS parity#18-bit width|18-bit mode]] (the two [[parity]] lines on that UNIBUS were recycled into two extra data lines). That UNIBUS had only an RH11-C, mounted in the main CPU rack (although apparently on its own backplane) to drive the MASSBUS to the disks. (Only MASSBUS disks were supported on that RH11-C, apparently both for performance reasons, and since 18-bit data storage was needed).
-The [[device controller]]s on the second UNIBUS were mounted in a [[BA11-K mounting box]], mounted in the main cabinet. These included a second RH11-C in DEC-supported systems, since [[Digital Equipment Corporation|DEC]] required a tape drive for loading [[diagnostic]]s; the usual choice was a [[TU45 magtape drive|TU45]] interfaced via a [[TM02 magtape controller|TM02]].
+The [[device controller]]s on the second UNIBUS were mounted in a [[BA11-K mounting box]], mounted in the main cabinet. These included a second RH11-C in DEC-supported systems, since DEC required a tape drive for loading [[diagnostic]]s; the usual choice was a [[TU45 magtape drive|TU45]] interfaced via a [[TM02 magtape controller|TM02]].
 ===CPU details===
-It was built out of [[LS TTL]] [[chip]]s, along with [[AMD 2901]] 4-bit-wide bit slice chips. The CPU was on four [[DEC card form factor|super hex]] cards:
+It was built out of [[LS TTL]] [[integrated circuit|chips]], along with [[AMD 2901]] 4-bit-wide bit slice chips. The CPU was on four [[DEC card form factor|super hex]] cards:
 * M8620 DPE - data path

← Older revision		Revision as of 13:36, 25 October 2022
Line 113:		Line 113:
	[[Category: PDP-10 Processors]]		[[Category: PDP-10 Processors]]
	[[Category: UNIBUS Processors]]		[[Category: UNIBUS Processors]]
		+	[[Category: DEC Documentation Errors]]