KT11-B Major State circuitry - Revision history

Jnc: Avoid redir

2023-07-02T16:24:38Z

Avoid redir

Jnc: move to K11-B specific cat

2022-10-11T20:20:22Z

move to K11-B specific cat

Jnc: +cat

2018-12-16T14:08:41Z

+cat

Jnc: Jnc moved page KT11-B Major State circutry to KT11-B Major State circuitry: Typo in name

2017-07-08T01:06:15Z

Jnc moved page KT11-B Major State circutry to KT11-B Major State circuitry: Typo in name

Jnc: link a few things

2016-12-26T14:25:48Z

link a few things

Jnc: copyedit

2016-11-08T02:20:51Z

copyedit

Jnc: not a shift reg

2016-09-30T04:01:49Z

not a shift reg

Jnc: Too big to put in Tech Man page

2016-09-30T04:00:01Z

Too big to put in Tech Man page

New page

This is a detailed description of the the circuitry that generates the major state of the KT11-B (page 12-1, lower left corner) - and in particular, how the state change signals (XSHL, XSHR) work.

The four NOR gates on the right (drawn as AND gates with inverted inputs) generate four individual major state lines (XSR0-3) from two bits (the two D flops); the top flop is the 010 bit, and the bottom flop is the 01 bit.

Note that the D flops are drawn with the top (Q) outputs labelled '1' - this
is because the outputs need to be inverted. So, logically speaking, the top output is 10(0) (i.e. when asserted, it means the high bit is 0), etc.

The four outputs (10(0), 10(1), 1(0) and 1(1)) are combined with XSHL and XSHR through an AND/OR network (actually all NANDS, so the un-named intermediate signals are logically inverted) which generates two signals, one for the D input of each flop:

* 10 flop: XSHR*1(1) + XSHL*1(0)
* 1 flop: XSHR*10(0) + XSHL*10(1)

(* = AND, + = OR; notation used throughout the KT11-B prints)

(Notice that this looks nothing like a conventional counter, where the new state of the high bit, after a count event, depends on the old state of the high bit as well as that of the low bit; these each depend only on the old state of the ''other'' bit.)

So, applying those functions to all the initial states, that produces the following table (initial state, flop inputs, new state):

{| class="wikitable"
! rowspan="2" style="text-align:center;" | State !! colspan="2" style="text-align:center;" | Inputs !! colspan="2" style="text-align:center;" | New State
|-
! L !! R !! L !! R
|-
| 00 || S- || -S || 10 || 01
|-
| 01 || -- || SS || 00 || 11
|-
| 10 || SS || -- || 11 || 00
|-
| 11 || -S || S- || 01 || 10
|}

So, a sequence of XSHL pulses will generate the following major state train:

00, 10, 11, 01, 00

and XSHR will produce:

00, 01, 11, 10, 00

Note that these Gray-code sequences. So from major state 0, one can go to 1 or 2; from 1, to 0 or 3; from 2, to 3 or 0; and from 3, to 1 or 2. The state diagram in the KT11-B Option Description document confirms this.

@@ Line 41: / Line 41: @@
 , 01, 11, 10, 00
-Note that these are [[Gray-code]] sequences. So from major state 0, one can go to 1 or 2; from 1, to 0 or 3; from 2, to 3 or 0; and from 3, to 1 or 2. The state diagram in the KT11-B Option Description document confirms this.
+Note that these are [[Gray code]] sequences. So from major state 0, one can go to 1 or 2; from 1, to 0 or 3; from 2, to 3 or 0; and from 3, to 1 or 2. The state diagram in the KT11-B Option Description document confirms this.
 [[Category: KT11-B]]

← Older revision		Revision as of 20:20, 11 October 2022
Line 43:		Line 43:
	Note that these are [[Gray-code]] sequences. So from major state 0, one can go to 1 or 2; from 1, to 0 or 3; from 2, to 3 or 0; and from 3, to 1 or 2. The state diagram in the KT11-B Option Description document confirms this.		Note that these are [[Gray-code]] sequences. So from major state 0, one can go to 1 or 2; from 1, to 0 or 3; from 2, to 3 or 0; and from 3, to 1 or 2. The state diagram in the KT11-B Option Description document confirms this.

−	[[Category: ~~PDP~~-~~11 Processors~~]]	+	[[Category: KT11-B]]

← Older revision		Revision as of 14:08, 16 December 2018
Line 42:		Line 42:

	Note that these are [[Gray-code]] sequences. So from major state 0, one can go to 1 or 2; from 1, to 0 or 3; from 2, to 3 or 0; and from 3, to 1 or 2. The state diagram in the KT11-B Option Description document confirms this.		Note that these are [[Gray-code]] sequences. So from major state 0, one can go to 1 or 2; from 1, to 0 or 3; from 2, to 3 or 0; and from 3, to 1 or 2. The state diagram in the KT11-B Option Description document confirms this.
		+
		+	[[Category: PDP-11 Processors]]

@@ Line 1: / Line 1: @@
-This is a detailed description of the the circuitry that generates the major state of the KT11-B (page 12-1, lower left corner) - and in particular, how the state change signals (XSHL, XSHR) work.
+This is a detailed description of the the circuitry that generates the major state of the [[KT11-B Paging Option|KT11-B]] (page 12-1, lower left corner) - and in particular, how the state change signals (XSHL, XSHR) work.
 The four NOR gates on the right (drawn as AND gates with inverted inputs) generate four individual major state lines (XSR0-3) from two bits (the two D flops); the top flop is the 010 bit, and the bottom flop is the 01 bit.
@@ Line 41: / Line 41: @@
 , 01, 11, 10, 00
-Note that these are Gray-code sequences. So from major state 0, one can go to 1 or 2; from 1, to 0 or 3; from 2, to 3 or 0; and from 3, to 1 or 2. The state diagram in the KT11-B Option Description document confirms this.
+Note that these are [[Gray-code]] sequences. So from major state 0, one can go to 1 or 2; from 1, to 0 or 3; from 2, to 3 or 0; and from 3, to 1 or 2. The state diagram in the KT11-B Option Description document confirms this.

← Older revision		Revision as of 02:20, 8 November 2016
Line 41:		Line 41:
	00, 01, 11, 10, 00		00, 01, 11, 10, 00

−	Note that these Gray-code sequences. So from major state 0, one can go to 1 or 2; from 1, to 0 or 3; from 2, to 3 or 0; and from 3, to 1 or 2. The state diagram in the KT11-B Option Description document confirms this.	+	Note that these are Gray-code sequences. So from major state 0, one can go to 1 or 2; from 1, to 0 or 3; from 2, to 3 or 0; and from 3, to 1 or 2. The state diagram in the KT11-B Option Description document confirms this.

← Older revision	Revision as of 01:06, 8 July 2017
(No difference)

← Older revision		Revision as of 04:01, 30 September 2016
Line 2:		Line 2:

	The four NOR gates on the right (drawn as AND gates with inverted inputs) generate four individual major state lines (XSR0-3) from two bits (the two D flops); the top flop is the 010 bit, and the bottom flop is the 01 bit.		The four NOR gates on the right (drawn as AND gates with inverted inputs) generate four individual major state lines (XSR0-3) from two bits (the two D flops); the top flop is the 010 bit, and the bottom flop is the 01 bit.
		+
		+	(Note that this circuity is not a shift register, as per the Option Description Section 4.3; it can produce 4 different states from 2 bits, not possible with a shift register.)

	Note that the D flops are drawn with the top (Q) outputs labelled '1' - this		Note that the D flops are drawn with the top (Q) outputs labelled '1' - this