KT11-B Paging Option - Revision history

Jnc: move to K11-B specific cat

2022-10-11T20:23:11Z

move to K11-B specific cat

← Older revision		Revision as of 20:23, 11 October 2022
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	* [http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/KT11-B/KT11-B_EngrDrws_Feb72.pdf KT11-B Engineering Drawings]		* [http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/KT11-B/KT11-B_EngrDrws_Feb72.pdf KT11-B Engineering Drawings]

	[[Category: ~~PDP~~-~~11 UNIBUS Processors~~]]		[[Category: KT11-B]]

Jnc: /* External links */ +KT11-B Option Description

2022-05-31T06:54:54Z

External links: +KT11-B Option Description

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	==External links==		==External links==

			* [http://www.bitsavers.org/pdf/dec/pdp11/1120/KT11-B_OD_Apr71.pdf KT11-B Option Description]
	* [http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/KT11-B/KT11-B_EngrDrws_Feb72.pdf KT11-B Engineering Drawings]		* [http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/KT11-B/KT11-B_EngrDrws_Feb72.pdf KT11-B Engineering Drawings]

	~~{{PDP-11}}~~		[[Category: PDP-11 UNIBUS Processors]]

	[[Category: PDP-11 Processors]]

Jnc: /* External links */ link KT11-B Engineering Drawings

2021-03-14T11:07:55Z

External links: link KT11-B Engineering Drawings

← Older revision		Revision as of 11:07, 14 March 2021
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	* [[KT11-B Technical Manual]]		* [[KT11-B Technical Manual]]

			==External links==

			* [http://ana-3.lcs.mit.edu/~jnc/tech/pdp11/KT11-B/KT11-B_EngrDrws_Feb72.pdf KT11-B Engineering Drawings]

	{{PDP-11}}		{{PDP-11}}

	[[Category: PDP-11 Processors]]		[[Category: PDP-11 Processors]]

Jnc: /* Implementation */ +links

2019-06-22T19:34:36Z

Implementation: +links

← Older revision		Revision as of 19:34, 22 June 2019
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	The KA11 CPU of the -11/20 is also [[KA11 changes for the KT11-B\|slightly modified]], and a [[KA11 changes for the KT11-B#KA/KT Interface\|cable]] carries additional signals between the KA11 and KT11-B.		The KA11 CPU of the -11/20 is also [[KA11 changes for the KT11-B\|slightly modified]], and a [[KA11 changes for the KT11-B#KA/KT Interface\|cable]] carries additional signals between the KA11 and KT11-B.

	A page entry cache in the KT11-B (invisible to software) holds the 8 most-recently-used page table entries. Cache entries are divided into an associative memory entry, which is 8 bits wide (7 bits of page number, and 1 Exec/User bit), and a scratchpad memory entry, 16 bits wide. (Although these would seem, logically, to be single extended-width registers, the two sections are actually stored in different parts of the hardware, which is why they are described as paired entries.) Scrachpad entries hold page table entries; each associative memory entry contains the page number for the related scratchpad entry.		A page entry [[cache]] in the KT11-B (invisible to software) holds the 8 most-recently-used page table entries. Cache entries are divided into an associative memory entry, which is 8 bits wide (7 bits of page number, and 1 Exec/User bit), and a scratchpad memory entry, 16 bits wide. (Although these would seem, logically, to be single extended-width registers, the two sections are actually stored in different parts of the hardware, which is why they are described as paired entries.) Scrachpad entries hold page table entries; each associative memory entry contains the page number for the related scratchpad entry.

	~~The scratchpad memory is also used to hold many of the KT11-B's registers (below).~~ An option increases the size of the cache to 24 entries, which can reduce the amount of memory bandwidth 'wasted' on cache refills. It requires an additional scratchpad memory, and a group of associative memories.		An option increases the size of the cache to 24 entries, which can reduce the amount of memory bandwidth 'wasted' on cache refills. It requires an additional scratchpad memory, and a group of associative memories. The base scratchpad memory is also used to hold many of the KT11-B's registers (below).

	On a fault, the copy of the page table entry in the cache is cleared; that way, if the OS modifies the page table, and re-starts the instruction which faulted, the KT11-B does not use an old (and likely outdated) cached page table entry. The entire cache is cleared whenever either page table register is modified; this is done by invalidating all cached entries by clearing the associative memories.		On a fault, the copy of the page table entry in the cache is cleared; that way, if the OS modifies the page table, and re-starts the instruction which faulted, the KT11-B does not use an old (and likely outdated) cached page table entry. The entire cache is cleared whenever either page table register is modified; this is done by invalidating all cached entries by clearing the associative memories.
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	===Debugging===		===Debugging===

	The KT11-B supports the standard DEC W130/W131 maintenance board set; it plugs into slot A14 of the KT11-B. The two switches:		The KT11-B supports the standard DEC [[KM11-A Maintenance Set\|W130/W131 maintenance board set]]; it plugs into slot A14 of the KT11-B. The two switches:

	* Enable the maintenance clock		* Enable the maintenance clock

Jnc: better cat

2018-12-16T22:02:19Z

better cat

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	{{PDP-11}}		{{PDP-11}}

	[[Category: ~~DEC~~ Processors]]		[[Category: PDP-11 Processors]]

Jnc: +cat, +links

2018-12-16T13:50:19Z

+cat, +links

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	The '''KT11-B Paging Option''' is a memory management option for the [[PDP-11/20]], produced by [[DEC]]'s Computer Special Systems group; it can provide a "multi-user, machine-language [[~~timesharing~~]] environment".		The '''KT11-B Paging Option''' is a [[memory management]] option for the [[PDP-11/20]], produced by [[Digital Equipment Corporation\|DEC]]'s Computer Special Systems group; it can provide a "[[multi-user]], machine-language [[time-sharing]] environment".

	It allows implementation of [[virtual memory]]; the [[address space]] is divided into [[page]]s, and when a reference it made to a page which is not 'resident' (i.e. present in physical [[main memory]]), the ~~computation~~ is stopped so the missing page can be made resident.		It allows implementation of [[virtual memory]]; the [[address space]] is divided into [[page]]s, and when a reference it made to a page which is not 'resident' (i.e. present in physical [[main memory]]), the [[instruction]] is stopped so the missing page can be made resident.

	It also allows the system to use up to 248 Kbytes of memory (the maximum allowed by the [[UNIBUS]]), although only a maximum of 64 KBytes is accessable (i.e. in the [[Central Processing Unit\|CPU]]'s address space) at any one time.		It also allows the system to use up to 248 Kbytes of memory (the maximum allowed by the [[UNIBUS]]), although only a maximum of 64 KBytes is accessable (i.e. in the [[Central Processing Unit\|CPU]]'s address space) at any one time.
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	{{PDP-11}}		{{PDP-11}}

			[[Category: DEC Processors]]

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2018-05-10T12:35:01Z

Buses: avoid redirs

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	* Beginning termination for that one, slots A/B04		* Beginning termination for that one, slots A/B04

	All devices must be moved 'down-stream' of the KT11 (apparently so that proper interrupt processing can be performed); this includes all devices that would normally be resident in the CPU backplane, including the console [[KL11]]/[[DL11]] and the [[KW11-L]] Line Time Clock.		All devices must be moved 'down-stream' of the KT11 (apparently so that proper interrupt processing can be performed); this includes all devices that would normally be resident in the CPU backplane, including the console [[KL11]]/[[DL11 asynchronous serial line interface\|DL11]] and the [[KW11-L Line Time Clock]].

	Since the latter is a single-height board which requires a specially-wired slot, a space is provided for it in the KT11-B backplane, at slot B09.		Since the latter is a single-height board which requires a specially-wired slot, a space is provided for it in the KT11-B backplane, at slot B09.

Jnc: /* See also */ Typo

2018-02-11T20:24:32Z

Jnc: Ad links, minor clarification

2017-12-17T01:07:25Z

Ad links, minor clarification

← Older revision		Revision as of 01:07, 17 December 2017
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	The '''KT11-B Paging Option''' is a memory management option for the [[PDP-11/20]], produced by [[DEC]]'s Computer Special Systems group; it can provide a "multi-user, machine-language [[timesharing]] environment".		The '''KT11-B Paging Option''' is a memory management option for the [[PDP-11/20]], produced by [[DEC]]'s Computer Special Systems group; it can provide a "multi-user, machine-language [[timesharing]] environment".

	It allows implementation of [[virtual memory]]; the [[address space]] is divided into [[page]]s, and when a reference it made to a page which is not 'resident' (i.e. present in physical [[main memory]]), the computation is stopped so the missing page can be made resident. It also allows the system to use up to 248 Kbytes of memory (the maximum allowed by the [[UNIBUS]]), although only a maximum of 64 KBytes is accessable (i.e. in the [[CPU]]'s address space) at any one time.		It allows implementation of [[virtual memory]]; the [[address space]] is divided into [[page]]s, and when a reference it made to a page which is not 'resident' (i.e. present in physical [[main memory]]), the computation is stopped so the missing page can be made resident.

			It also allows the system to use up to 248 Kbytes of memory (the maximum allowed by the [[UNIBUS]]), although only a maximum of 64 KBytes is accessable (i.e. in the [[Central Processing Unit\|CPU]]'s address space) at any one time.

	Finally, hardware features prevent any user from interfering with the overall operation of the system. It does this by providing two modes for the CPU, 'User' and 'Exec', with certain operations (e.g. halting the machine) being dis-allowed in User mode.		Finally, hardware features prevent any user from interfering with the overall operation of the system. It does this by providing two modes for the CPU, 'User' and 'Exec', with certain operations (e.g. halting the machine) being dis-allowed in User mode.

	By proper programming, the virtual memory (with separate address spaces for Exec and User mode) may be set up so that user ~~processes~~ cannot interfere with each other's memory, or the [[operating system]]'s.		By proper programming, the virtual memory (with separate address spaces for Exec and User mode) may be set up so that user [[process]]es cannot interfere with each other's memory, or the [[operating system]]'s.

	The KT11-B is composed of a large number of ~~[[DEC card form factor\|single width]]~~ [[FLIP CHIP]]s, most of them simple, generic ones; they are plugged into a custom [[wire-wrap]]ped [[backplane]].		The KT11-B is composed of a large number of [[FLIP CHIP]]s, most of them simple, generic [[DEC card form factor\|single width]] ones; they are plugged into a custom [[wire-wrap]]ped [[backplane]].

	===Additional features===		===Additional features===
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	Individual pages may be marked 'Private', which means that only access from code running in Private pages is allowed; i.e. information in such pages is hidden from code in 'Public' pages. This allows the use of proprietary software, while preventing it from being copied in an un-authorized manner.		Individual pages may be marked 'Private', which means that only access from code running in Private pages is allowed; i.e. information in such pages is hidden from code in 'Public' pages. This allows the use of proprietary software, while preventing it from being copied in an un-authorized manner.

	Control may be transferred from code running in Public pages to Private pages only at 'entry points', locations which contain a particular instruction ("BR .+2").		Control may be transferred from code running in Public pages to Private pages only at 'entry points', locations which contain a particular instruction ("BR .+2"); a valid [[instruction]], but one which normal code is unlikely to contain.

	==Architecture==		==Architecture==

Jnc: /* Implementation */ better word

2017-07-25T21:49:43Z

Implementation: better word

← Older revision		Revision as of 21:49, 25 July 2017
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	The KA11 CPU of the -11/20 is also [[KA11 changes for the KT11-B\|slightly modified]], and a [[KA11 changes for the KT11-B#KA/KT Interface\|cable]] carries additional signals between the KA11 and KT11-B.		The KA11 CPU of the -11/20 is also [[KA11 changes for the KT11-B\|slightly modified]], and a [[KA11 changes for the KT11-B#KA/KT Interface\|cable]] carries additional signals between the KA11 and KT11-B.

	A page entry cache in the KT11-B (invisible to software) holds the 8 most-recently-used page table entries. Cache entries are divided into an associative memory, which is 8 bits wide (7 bits of page number, and 1 Exec/User bit), and a scratchpad memory entry, 16 bits wide. (Although these seem, logically, to be single extended-width registers, the two ~~parts~~ are actually stored in different parts of the hardware, which is why they are described as paired ~~parts~~.) Scrachpad entries hold page table entries; each associative memory entry contains the page number for the related scratchpad entry.		A page entry cache in the KT11-B (invisible to software) holds the 8 most-recently-used page table entries. Cache entries are divided into an associative memory entry, which is 8 bits wide (7 bits of page number, and 1 Exec/User bit), and a scratchpad memory entry, 16 bits wide. (Although these would seem, logically, to be single extended-width registers, the two sections are actually stored in different parts of the hardware, which is why they are described as paired entries.) Scrachpad entries hold page table entries; each associative memory entry contains the page number for the related scratchpad entry.

	The scratchpad memory is also used to hold many of the KT11-B's registers (below). An option increases the size of the cache to 24 entries, which can reduce the amount of memory bandwidth 'wasted' on cache refills. It requires an additional scratchpad memory, and a group of associative memories.		The scratchpad memory is also used to hold many of the KT11-B's registers (below). An option increases the size of the cache to 24 entries, which can reduce the amount of memory bandwidth 'wasted' on cache refills. It requires an additional scratchpad memory, and a group of associative memories.

← Older revision		Revision as of 20:24, 11 February 2018
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	Memory operations to this register are performed through to the User mode address given in the KTAD; this allows the operating system to perform memory cycles just as code in User mode would, without needing to do a complex emulation.		Memory operations to this register are performed through to the User mode address given in the KTAD; this allows the operating system to perform memory cycles just as code in User mode would, without needing to do a complex emulation.

	==See ~~alsoo~~==		==See also==

	* [[KT11-B Technical Manual]]		* [[KT11-B Technical Manual]]

	{{PDP-11}}		{{PDP-11}}