KT11-B Technical Manual - Revision history

Jnc: rm bloat

2023-07-02T16:22:31Z

rm bloat

Jnc: /* High-Level Overview */ clarify

2023-07-02T16:16:38Z

‎High-Level Overview: clarify

Jnc: Move to new, specific cat

2022-10-11T20:12:45Z

Move to new, specific cat

Jnc: /* Card Information */ M259 and M826 unknown

2021-03-14T09:58:06Z

‎Card Information: M259 and M826 unknown

Jnc: link 1st instance

2020-07-26T20:29:54Z

link 1st instance

Jnc: /* Module Locations */ typo

2020-07-26T20:27:44Z

‎Module Locations: typo

Jnc: /* Signal Dictionary */ typo

2020-07-26T20:18:38Z

‎Signal Dictionary: typo

Jnc: /* Buffered Signals and Main Logic */ +link

2019-06-22T19:36:06Z

‎Buffered Signals and Main Logic: +link

Jnc: /* Timing Logic */ +link

2019-06-22T19:30:19Z

‎Timing Logic: +link

Jnc: +cat

2018-12-16T14:09:02Z

+cat

← Older revision		Revision as of 16:22, 2 July 2023
Line 593:		Line 593:

	Shown on page 13-1, this is actually not a part of the KT11-B; rather, it is the Maintenance Card, which must plug into the KT11-B's backplane.		Shown on page 13-1, this is actually not a part of the KT11-B; rather, it is the Maintenance Card, which must plug into the KT11-B's backplane.
−
−	~~{{PDP-11}}~~

	[[Category: KT11-B]]		[[Category: KT11-B]]

@@ Line 11: / Line 11: @@
 The heart of the KT11-B is the scratchpad memory, which is used to hold both cached [[page table]] entries, and also most of the KT11-B registers.
-(Since the KT11-B does not contain any internal registers to which the CPU does not have access, the term 'register' hereinafter refers to any of the registers visible to the CPU in the KT11-B.)
+(Since the KT11-B does not contain any internal registers to which the CPU does not have access, the term 'register' hereinafter refers to any of the registers in the KT11-B visible to the CPU.)
 The scratchpad has a built-in [[address]] multiplexor, so address lines from a variety of sources are all fed directly into it; see the "Keys and Associative Memory" section below, for details. A latching input data multiplexor is provided to select among data from a number of sources for storage in the scratchpad.
-One of the possible inputs to that mux is the output of the scratchpad itself: since there is no latch on the output of the scratchpad, the ability to select its output, and then latch it, is sometimes used to hold data from the scratchpad for other users. (E.g. the comparator which checks to see whether cycles are in the Simple part of the [[address space]].)
+One of the possible inputs to that mux is the output of the scratchpad itself: since there is no latch on the output of the scratchpad, the ability to select its output, and then latch it, is sometimes used to hold data from the scratchpad for other users. (E.g. the comparator which checks to see whether cycles are in the 'Simple' part of the [[address space]].)
 A uni-directional address [[bus]] runs from the CPU's UNIBUS to the device UNIBUS; the KT11-B internals, such as the scratchpad, may also generate addresses (e.g. for loading page table entries). An address multiplexor for this bus can perform non-trivial selections (e.g. getting high address bits - i.e. physical page numbers - from scratchpad output, and low bits - i.e. addresses within a page - from the incoming address bus).
@@ Line 23: / Line 23: @@
 The majority of the signals that control the operation of the buses, multiplexors, etc. are generated by random [[logic]] - a group of [[gate]]s (and sometimes [[flip-flop]]s as well); it is usually necessary to inspect the actual drawings to ascertain how any major data-handling item is controlled.
-If the optional extended [[cache]] (holding an additional scatchpad memory, and an array of associative memories) is installed, it functions in much the same way as the base cache, except that since it does not hold any registers, its role is nowhere near as central as that of the main scratchpad.
+If the optional extended [[cache]] (holding an additional scratchpad memory, and an array of associative memories) is installed, it functions in much the same way as the base cache, except that since it does not hold any registers, its role is nowhere near as central as that of the main scratchpad.
 ===States===

← Older revision		Revision as of 20:12, 11 October 2022
Line 596:		Line 596:
	{{PDP-11}}		{{PDP-11}}

−	[[Category: ~~PDP~~-~~11 Processors~~]]	+	[[Category: KT11-B]]

@@ Line 554: / Line 554: @@
 ==Card Information==
-The drawings contain a number of different FLIP CHIPs as blocks, without showing individual details; information about them is given here.
+The drawings contain a number of different FLIP CHIPs as blocks, without showing individual details; information about them is given here. (Internal details of the M259 and M826 are currently unknown; unless examples are found, so that they can be reverse engineered, they will probably remain so.)
 ===M167=== <!-- RS64-MM -->

@@ Line 348: / Line 348: @@
 * The KT11-B Control and Maintenance registers
-The left and center of the third sheet contains the other half of the data mux; the right shows the KW11-L Line Time Clock card.
+The left and center of the third sheet contains the other half of the data mux; the right shows the [[KW11-L Line Time Clock]] card.
 ===Keys and Associative Memory===
@@ Line 584: / Line 584: @@
 ===M787===
-Shown on page 7-3, this is actually not a part of the KT11-B; rather, it is the [[KW11-L Line Time Clock]], which must reside in the KT11-B's backplane.
+Shown on page 7-3, this is actually not a part of the KT11-B; rather, it is the KW11-L Line Time Clock, which must reside in the KT11-B's backplane.
 ===M826=== <!-- -->

@@ Line 547: / Line 547: @@
 * % = Optional
-* $ = Not part of KT11-D
+* $ = Not part of KT11-B
 * @ = Cable

@@ Line 247: / Line 247: @@
 * FETCH: In 'Fetch' major state
 * ISR 7: Bit 7 of the current instruction
-* ISR 12: Bit 7 of the current instruction
+* ISR 12: Bit 12 of the current instruction
 * JSR: Current instruction is 'JSR'
 * RTI: Current instruction is 'RTI'

@@ Line 398: / Line 398: @@
 ===Buffered Signals and Main Logic===
-The left side shows the W130 Maintenance Card; the top left and center contain buffering for various internal signals; the right contains buffering for the high 9 bits (i.e. the page number) of the internal address bus.
+The left side shows the [[KM11-A Maintenance Set|W130 Maintenance Card]]; the top left and center contain buffering for various internal signals; the right contains buffering for the high 9 bits (i.e. the page number) of the internal address bus.
 ===Extended Associative Memory===

@@ Line 388: / Line 388: @@
 The top and lower right contain gates which combine major and minor state lines into signals for each individual state.
-The lower left contains the 2-bit counter (built out of two D flops, and associated circuitry) which produces the major state; and also logic to produce major state signals. Note that the two flops (and their input circuitry) don't form a straight binary counter, but rather a Gray-code counter. So, a sequence of XSHL pulses will generate the following major state sequence:
+The lower left contains the 2-bit counter (built out of two D flops, and associated circuitry) which produces the major state; and also logic to produce major state signals. Note that the two flops (and their input circuitry) don't form a straight binary counter, but rather a [[Gray code]] counter. So, a sequence of XSHL pulses will generate the following major state sequence:
 , 10, 11, 01, 00

← Older revision		Revision as of 14:09, 16 December 2018
Line 595:		Line 595:

	{{PDP-11}}		{{PDP-11}}
		+
		+	[[Category: PDP-11 Processors]]