KT11-C Memory Management Unit - Revision history

Jnc: Better cat

2022-10-12T00:38:27Z

Better cat

Jnc: /* External links */ +man, eng drws

2022-03-06T16:47:34Z

‎External links: +man, eng drws

Jnc: kt11-b too unrelated

2020-04-11T16:31:09Z

kt11-b too unrelated

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2019-01-21T13:47:15Z

wrong name

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2019-01-21T13:45:05Z

typo,

Jnc: +cat

2018-12-19T23:19:12Z

+cat

Jnc: Proper cat

2018-10-19T22:51:28Z

Proper cat

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2018-05-14T00:33:07Z

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Jnc: A start

2018-05-06T15:08:57Z

A start

New page

The '''KT11-C Memory Management Unit''' is the [[memory management]] option for the [[PDP-11/45]]. It implements the full [[PDP-11 Memory Management]] architecture; in fact, the KT11-C is the archtype for PDP-11 memory management units.

The KT11-C consists of two [[DEC card form factor|hex]] cards:

* M8107 Segmentation Address Paths

and either:

* M8108 Segmentation Status Registers

or:

* M8108-YA Segmentation Status Registers

The M8108 board is found in the [[KB11-A CPU]] variant of the -11/45, and the M8108-YA in [[KB11-D CPU]] variant.

They both plug into pre-wired slots in the [[Central Processing Unit|CPU]] [[backplane]].

When the KT11-C is not present, the CPU must have an M8116 Segmentation Jumper Board present instead.

==See also==

* [[KT11-B Paging Option]]

{{stub}}

{{pdp-11}}

@@ Line 18: / Line 18: @@
 When the KT11-C is not present, the CPU must have an M8116 Segmentation Jumper Board present instead.
 ==External links==
@@ Line 25: / Line 29: @@
 * [http://www.bitsavers.org/pdf/dec/pdp11/1145/KT11C_Schem.pdf KT11-C memory management unit engineering drawings] (KT11C-1-A)
 * [http://www.bitsavers.org/pdf/dec/pdp11/1145/KT11-C_Memory_Management_Unit_Engineering_Drawings_Dec75.pdf  KT11-C memory management unit engineering drawings] (KT11C-2-B)
 {{semi-stub}}
-[[Category: PDP-11 Processors]]
+[[Category: PDP-11 UNIBUS Processors]]

@@ Line 18: / Line 18: @@
 When the KT11-C is not present, the CPU must have an M8116 Segmentation Jumper Board present instead.
 ==See also==
@@ Line 24: / Line 31: @@
 {{semi-stub}}
 [[Category: PDP-11 Processors]]

← Older revision		Revision as of 16:31, 11 April 2020
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	==See also==		==See also==

−	* [[KT11-B Paging Option]]
	* [[KT11-D Memory Management Unit]]		* [[KT11-D Memory Management Unit]]

@@ Line 22: / Line 22: @@
 * [[KT11-B Paging Option]]
-* [[KT11-D Paging Option]]
+* [[KT11-D Memory Management Unit]]
 {{semi-stub}}

@@ Line 1: / Line 1: @@
-The '''KT11-C Memory Management Unit''' is the [[memory management]] option for the [[PDP-11/45]]. It implements the full [[PDP-11 Memory Management]] architecture; in fact, the KT11-C is the archtype for PDP-11 memory management units.
+The '''KT11-C Memory Management Unit''' is the [[memory management]] option for the [[PDP-11/45]]. It implements the full [[PDP-11 Memory Management]] architecture; in fact, the KT11-C is the archetype for PDP-11 memory management units.
 The KT11-C consists of two [[DEC card form factor|hex]] cards:
@@ Line 22: / Line 22: @@
 * [[KT11-B Paging Option]]
 {{semi-stub}}

← Older revision		Revision as of 23:19, 19 December 2018
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	{{PDP-11}}		{{PDP-11}}
		+
		+	[[Category: PDP-11 Processors]]

@@ Line 23: / Line 23: @@
 * [[KT11-B Paging Option]]
-{{stub}}
+{{semi-stub}}
 {{PDP-11}}

← Older revision		Revision as of 00:33, 14 May 2018
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	{{stub}}		{{stub}}

−	{{~~pdp~~-11}}	+	{{PDP-11}}