KTJ11-B UNIBUS adapter - Revision history

Jnc: Clarify; typos

2024-10-08T11:16:17Z

Clarify; typos

Jnc: Oops, didn't write a complete sentence in the intro

2024-10-07T23:07:48Z

Oops, didn't write a complete sentence in the intro

Jnc: Move backplane details to separate backplane page; cover DMA cache

2024-10-07T23:02:56Z

Move backplane details to separate backplane page; cover DMA cache

Jnc: /* External links */ +PDP-11 Systems Handbook

2024-10-07T22:18:42Z

‎External links: +PDP-11 Systems Handbook

Jnc: +New category

2024-02-06T14:35:44Z

+New category

Jnc: /* External links */ better cat

2022-12-06T00:59:34Z

‎External links: better cat

Jnc: /* External links */ +manual

2022-12-06T00:58:31Z

‎External links: +manual

Jnc: /* Backplane details */ link QBUS grant card

2022-10-11T14:54:07Z

‎Backplane details: link QBUS grant card

Jnc: /* External links */ +cat

2022-10-11T14:42:58Z

‎External links: +cat

Jnc: +FMPS

2021-12-24T13:41:20Z

+FMPS

@@ Line 7: / Line 7: @@
 ==Technical details==
-The KTJ11-B contains a [cache]], to increase the efficiency of [[Direct Memory Access|DMA]] transfers on the UNIBUS; generally, two DMA red cycles on the UNIBUS result in a single PMI bus read operation. The cache contains 32 [[word]]-width entries, arranged into 4 independent 8-word sets; the KTJ11-B can thus handle 4 simultaneous DMA operations on the UNIBUS efficiently.
+The KTJ11-B contains a [[cache]], to increase the efficiency of [[Direct Memory Access|DMA]] transfers on the UNIBUS; generally, two DMA read cycles on the UNIBUS result in a single PMI bus read operation. The cache contains 32 [[word]]-width entries, arranged into 4 independent 8-word sets; the KTJ11-B can thus handle up to 4 simultaneous DMA operations on the UNIBUS efficiently.
 ==External links==
@@ Line 15: / Line 15: @@
 * [http://www.bitsavers.org/pdf/dec/pdp11/1184/MP-02015-01_11-84_Maintenance_Print_Set_198412.pdf 11/84 Field Maintenance Print Set (MP-02015-001)] - Contains KTJ11-B Field Maintenance Print Set (MP-02010-01) on pp. 127-156
 [[Category: UNIBUS]]
 [[Category: Private Memory Interconnect]]

@@ Line 1: / Line 1: @@
 [[Image:KTJ11-B.jpg|300px|thumb|right|KTJ11-B board]]
-The '''KTJ11-B UNIBUS adaptor''' is used with the [[KDJ11-B CPU|KDJ11-B]] and [[KDJ11-E CPU|KDJ11-E]] [[QBUS]] [[Central Processing Unit|CPU]] cards in the special [[KDJ11 PMI/UNIBUS backplane]] to add [[UNIBUS]] capability to systems built around those cards, the [[PDP-11/84]] and [[PDP-11/94]] systems respectively. It converts the native [[Private Memory Interconnect]] (PMI) [[bus]] supported by these
+The '''KTJ11-B UNIBUS adaptor''' is used with the [[KDJ11-B CPU|KDJ11-B]] and [[KDJ11-E CPU|KDJ11-E]] [[QBUS]] [[Central Processing Unit|CPU]] cards in the special [[KDJ11 PMI/UNIBUS backplane]] to add [[UNIBUS]] capability to systems built around those cards; the [[PDP-11/84]] and [[PDP-11/94]] systems respectively. It converts the native [[Private Memory Interconnect]] (PMI) [[bus]] supported by these CPUs to the [[Digital Equipment Corporation|DEC]]-standard UNIBUS.
 It is a [[DEC card form factor|hex-height]] board ('''M8191'''), and can only plug into the special [[backplane]], unique to those systems, which is wired to support it.

@@ Line 1: / Line 1: @@
 [[Image:KTJ11-B.jpg|300px|thumb|right|KTJ11-B board]]
-The '''KTJ11-B UNIBUS adaptor''' is used with the [[KDJ11-B CPU|KDJ11-B]] and [[KDJ11-E CPU|KDJ11-E]] [[QBUS]] [[Central Processing Unit|CPU]] cards to add [[UNIBUS]] capability to systems built around those CPU cards, the [[PDP-11/84]] and [[PDP-11/94]] systems respectively.
+The '''KTJ11-B UNIBUS adaptor''' is used with the [[KDJ11-B CPU|KDJ11-B]] and [[KDJ11-E CPU|KDJ11-E]] [[QBUS]] [[Central Processing Unit|CPU]] cards in the special [[KDJ11 PMI/UNIBUS backplane]] to add [[UNIBUS]] capability to systems built around those cards, the [[PDP-11/84]] and [[PDP-11/94]] systems respectively. It converts the native [[Private Memory Interconnect]] (PMI) [[bus]] supported by these
-It is a [[DEC card form factor|hex-height]] board ('''M8191'''), and can only plug into a special [[backplane]], unique to those systems, which is wired to support it.
+It is a [[DEC card form factor|hex-height]] board ('''M8191'''), and can only plug into the special [[backplane]], unique to those systems, which is wired to support it.
-==Backplane details==
+==Technical details==
-The custom 12+1 slot backplane used by the KTJ11-B was half QBUS, and half UNIBUS (the 13th 'slot' is not a full slot, it only has a [[DEC edge connector contact identification|connector]] for one set of fingers). It has [[Private Memory Interconnect]] (PMI) bus slots at the top (for the CPU and [[main memory]] cards), a special slot in the middle for the KTJ11-B, and then UNIBUS slots.
+The KTJ11-B contains a [cache]], to increase the efficiency of [[Direct Memory Access|DMA]] transfers on the UNIBUS; generally, two DMA red cycles on the UNIBUS result in a single PMI bus read operation. The cache contains 32 [[word]]-width entries, arranged into 4 independent 8-word sets; the KTJ11-B can thus handle 4 simultaneous DMA operations on the UNIBUS efficiently.
 ==External links==

← Older revision		Revision as of 22:18, 7 October 2024
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	* [http://www.bitsavers.org/pdf/dec/pdp11/1184/EK-1184E-TM-001_Dec87.pdf PDP-11/84 System Technical and Reference Manual] (EK-1184E-TM-001) - the KTJ11-B is covered on pp. 68-85 of the PDF		* [http://www.bitsavers.org/pdf/dec/pdp11/1184/EK-1184E-TM-001_Dec87.pdf PDP-11/84 System Technical and Reference Manual] (EK-1184E-TM-001) - the KTJ11-B is covered on pp. 68-85 of the PDF
		+	* [http://www.bitsavers.org/pdf/dec/pdp11/handbooks/PDP-11_Systems_Handbook_1987.pdf PDP-11 Systems Handbook] (EB 29317 41) - the KTJ11-B is covered on pp. 143-147 of the PDF
	* [http://www.bitsavers.org/pdf/dec/pdp11/1184/MP-02015-01_11-84_Maintenance_Print_Set_198412.pdf 11/84 Field Maintenance Print Set (MP-02015-001)] - Contains KTJ11-B Field Maintenance Print Set (MP-02010-01) on pp. 127-156		* [http://www.bitsavers.org/pdf/dec/pdp11/1184/MP-02015-01_11-84_Maintenance_Print_Set_198412.pdf 11/84 Field Maintenance Print Set (MP-02015-001)] - Contains KTJ11-B Field Maintenance Print Set (MP-02010-01) on pp. 127-156

← Older revision		Revision as of 14:35, 6 February 2024
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	[[Category: PDP-11 UNIBUS Processors]]		[[Category: PDP-11 UNIBUS Processors]]
	[[Category: UNIBUS]]		[[Category: UNIBUS]]
		+	[[Category: Private Memory Interconnect]]

@@ Line 91: / Line 91: @@
 * [http://www.bitsavers.org/pdf/dec/pdp11/1184/MP-02015-01_11-84_Maintenance_Print_Set_198412.pdf 11/84 Field Maintenance Print Set (MP-02015-001)] - Contains KTJ11-B Field Maintenance Print Set (MP-02010-01) on pp. 127-156
-[[Category: PDP-11 Processors]]
+[[Category: PDP-11 UNIBUS Processors]]
 [[Category: UNIBUS]]

@@ Line 25: / Line 25: @@
 Note that the PMI slots do not have the [[Private Memory Interconnect#CD interconnect details|bottom-up]] ordering of PMI-capable slots in a Q22/CD backplane, but are wired as a true bus, allowing the 'CPU, memory, memory' insertion ordering seen here.
-Note also that in the normal configuration (see below for details), the QBUS [[bus grant line]]s are not routed through the memory slots, so if one of these slot is unused, there is no need for a [[jumper]] card in that slot.
+Note also that in the normal configuration (see below for details), the QBUS [[bus grant line]]s are not routed through the memory slots, so if one of these slot is unused, there is no need for a [[M9047 grant continuity card]] in that slot.
 As a further feature, on most UNIBUS backplanes, the 'NPG' ([[Direct Memory Access|DMA]] grant line) signal is carried across unused slots by wire jumpers on [[wire-wrap]] pins on the back side of the backplane; on the -11/84 backplane, they are brought out to a [[Dual Inline Package|DIP]] switch on the MDM module, for easier configuration changes.

← Older revision		Revision as of 14:42, 11 October 2022
Line 91:		Line 91:

	[[Category: PDP-11 Processors]]		[[Category: PDP-11 Processors]]
		+	[[Category: UNIBUS]]

@@ Line 86: / Line 86: @@
 Interrupt cycles are more problematic; the assertion of the interrupt level on the BDAL lines (step 1a) will probably pass, but step 6 (assertion of BSACK) may be an issue, since the device will want to assert BRPLY instead (BSACK is not used in a QBUS interrupt), and the CPU may not do the right thing.
-{{PDP-11}}
+==External links==
 [[Category: PDP-11 Processors]]