KUV11 Writeable Control Store - Revision history

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Removed duplicate link

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‎External links

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A pretty good start

New page

The '''KUV11 Writeable Control Store''' is an option for the [[LSI-11]] which provides a [[user]]-[[programmable]] [[microcode]] [[memory]] extension, along with some [[hardware]] aids to [[debug]]ging micro-[[program]]s. It allows additional, custom [[instruction]]s to be added to the [[PDP-11]] [[instruction set]].

It consists of a [[DEC card form factor|quad]] [[printed circuit board|card]] (M8018) which plugs into the [[QBUS]] [[backplane]] close to the [[Central Processing Unit|CPU]] card, and a [[flat cable]] which runs from the KUV11 to a free micro-[[Read-only memory|ROM]] [[chip socket]] on the CPU card, and gives the KUV11 access to the micro-instruction [[bus]].

The micro-store consists of 24 1Kx1 high-speed [[static RAM]] [[integrated circuit|chips]], along with other hardware. The LSI-11 micro-[[word]] is 22 bits long; the extra two bits are fed to backplane pins (AE1 and AF1) to provide high-speed controls. A [[Dual Inline Package|DIP]] switch on the KUV11 controls where the micro-store appears in the micro-[[address space]].

The micro-words themseves are fed to the LSI-11 over the cable; the LSI-11 does not have the ability to write the micro-store contents over that cable, but has read-write access to it via the QBUS. That bus also provides access to a number of control [[register]]s on the KUV11.

The principle hardware debugging aid is the 'micro-[[address]] trace [[Random Access Memory|RAM]]', which is a 16-entry record of consecutive micro-addresses emitted as the micro-program runs, which can be frozen under program control, using one of the two extra bits in the micro-word.

==Further reading==

* ''LSI-11 WCS User's Guide'', EK-KUV11-TM-001

{{PDP-11}}

@@ Line 16: / Line 16: @@
 ** [http://www.bitsavers.org/pdf/dec/pdp11/1103/M8018_LSI-11_WCS_Schematic.pdf Writeable Control Store Engineering Drawings]
 * [http://www.vaxarchive.org/hardware/pdp11/wcsrc.tar WCS reference card] (images in TAR file)
 [[Category: PDP-11 QBUS Processors]]

@@ Line 16: / Line 16: @@
 ** [http://www.bitsavers.org/pdf/dec/pdp11/1103/M8018_LSI-11_WCS_Schematic.pdf Writeable Control Store Engineering Drawings]
 * [http://www.vaxarchive.org/hardware/pdp11/wcsrc.tar WCS reference card] (images in TAR file)
 {{PDP-11}}
-[[Category: PDP-11 Processors]]
+[[Category: PDP-11 QBUS Processors]]

@@ Line 18: / Line 18: @@
 [[Category: PDP-11 Processors]]
 {{PDP-11}}
 [[Category: PDP-11 Processors]]

@@ Line 9: / Line 9: @@
 The principle hardware debugging aid is the 'micro-[[address]] trace [[Random Access Memory|RAM]]', which is a 16-entry record of consecutive micro-addresses emitted as the micro-program runs, which can be frozen under program control, using one of the two extra bits in the extended micro-word.
-==Further reading==
+==External links==
-* ''LSI-11 WCS User's Guide'', EK-KUV11-TM-001
+* [http://www.bitsavers.org/pdf/dec/pdp11/1103/ PDP-11/03] - documentation at [[Bitsavers]]
 ==External links==

← Older revision		Revision as of 14:10, 16 December 2018
Line 14:		Line 14:

	{{PDP-11}}		{{PDP-11}}
		+
		+	[[Category: PDP-11 Processors]]

@@ Line 3: / Line 3: @@
 It consists of a [[DEC card form factor|quad]] [[printed circuit board|card]] (M8018) which plugs into the [[QBUS]] [[backplane]] close to the [[Central Processing Unit|CPU]] card, and a [[flat cable]] which runs from the KUV11 to a free micro-[[Read-only memory|ROM]] [[chip socket]] on the CPU card, and gives the KUV11 access to the micro-instruction [[bus]].
-The micro-store consists of 24 1Kx1 high-speed [[static RAM]] [[integrated circuit|chips]], along with other hardware. The LSI-11 micro-[[word]] is 22 bits long; the extra two bits are fed to backplane pins (AE1 and AF1) to provide high-speed controls. A [[Dual Inline Package|DIP]] switch on the KUV11 controls where the micro-store appears in the micro-[[address space]].
+The micro-store consists of 24 1Kx1 high-speed [[static RAM]] [[integrated circuit|chips]]. The LSI-11 micro-[[word]] is 22 bits long; the extra two bits are fed to backplane pins (AE1 and AF1) to provide high-speed controls. A [[Dual Inline Package|DIP]] switch on the KUV11 controls where the micro-store appears in the micro-[[address space]].
 The micro-words themseves are fed to the LSI-11 over the cable; the LSI-11 does not have the ability to write the micro-store contents over that cable, but has read-write access to it via the QBUS. That bus also provides access to a number of control [[register]]s on the KUV11.
-The principle hardware debugging aid is the 'micro-[[address]] trace [[Random Access Memory|RAM]]', which is a 16-entry record of consecutive micro-addresses emitted as the micro-program runs, which can be frozen under program control, using one of the two extra bits in the micro-word.
+The principle hardware debugging aid is the 'micro-[[address]] trace [[Random Access Memory|RAM]]', which is a 16-entry record of consecutive micro-addresses emitted as the micro-program runs, which can be frozen under program control, using one of the two extra bits in the extended micro-word.
 ==Further reading==