LSI-11 CPUs - Revision history

Jnc: /* External links */ +Frain page

2025-05-31T12:56:38Z

‎External links: +Frain page

Jnc: /* Further reading */ +Wake-up Circuit Implementations

2024-07-29T15:03:53Z

‎Further reading: +Wake-up Circuit Implementations

Jnc: /* Further reading */ +System Differences - LSI-11 vs. LSI-11/23

2024-07-27T23:53:54Z

‎Further reading: +System Differences - LSI-11 vs. LSI-11/23

Jnc: Avoid redir

2024-04-06T14:35:37Z

Avoid redir

Jnc: /* External links */ Narrow category

2022-10-11T17:34:00Z

‎External links: Narrow category

Jnc: +link

2021-12-07T16:03:30Z

+link

Jnc: /* External links */ +LSI-11chapter in 'Computer Engineering'

2021-12-07T15:30:36Z

‎External links: +LSI-11chapter in 'Computer Engineering'

Jnc: Add speed info

2021-11-15T23:38:01Z

Add speed info

Jnc: Does in fact work with Q18

2020-05-02T18:36:59Z

Does in fact work with Q18

Jnc: Move limitations here frrom chip set page

2019-08-19T18:16:46Z

Move limitations here frrom chip set page

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 * Mark J. Sebern, [http://gordonbell.azurewebsites.net/Computer_Engineering/00000323.htm A Minicomputer-Compatible Microcomputer System: The DEC LSI-11], in C. Gordon Bell, J. Craig Mudge, John. E. McNamara, ''Computer Engineering: A DEC View of Hardware Systems Design'', Digital Press, Bedford, 1978
 {{Nav PDP-11}}
 [[Category: PDP-11 QBUS Processors]]

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 ==Further reading==
-* ''System Differences - LSI-11 vs. LSI-11/23'', MicroNote #049
+* ''System Differences - LSI-11 vs. LSI-11/23'', [[MicroNote]] #049
 ==External links==

← Older revision		Revision as of 23:53, 27 July 2024
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	* [[KDF11 CPUs]]		* [[KDF11 CPUs]]
		+
		+	==Further reading==
		+
		+	* ''System Differences - LSI-11 vs. LSI-11/23'', MicroNote #049

	==External links==		==External links==

@@ Line 27: / Line 27: @@
 * Mark J. Sebern, [http://gordonbell.azurewebsites.net/Computer_Engineering/00000323.htm A Minicomputer-Compatible Microcomputer System: The DEC LSI-11], in C. Gordon Bell, J. Craig Mudge, John. E. McNamara, ''Computer Engineering: A DEC View of Hardware Systems Design'', Digital Press, Bedford, 1978
-{{PDP-11s}}
+{{Nav PDP-11}}
 [[Category: PDP-11 QBUS Processors]]

← Older revision		Revision as of 17:34, 11 October 2022
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	{{PDP-11s}}		{{PDP-11s}}

−	[[Category: PDP-11 ~~Processors]]~~	+	[[Category: PDP-11 QBUS Processors]]
−	~~[[Category:~~ QBUS Processors]]

← Older revision		Revision as of 16:03, 7 December 2021
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−	The '''LSI-11 CPUs''' were DEC's first cost-reduced [[PDP-11]] [[Central Processing Unit\|CPUs]], using a [[microprocessor]] (the [[LSI-11 chip set]]). They also used a new [[bus]], the [[QBUS]].	+	The '''LSI-11 CPUs''' were [[Digital Equipment Corporation\|DEC]]'s first cost-reduced [[PDP-11]] [[Central Processing Unit\|CPUs]], using a [[microprocessor]] (the [[LSI-11 chip set]]). They also used a new [[bus]], the [[QBUS]].

	The basic [[clock]] μcycle is 350 nsec; simple [[register]]-register [[instruction]]s (e.g. MOV, ADD) took 3.5 μseconds; depending on the exact [[operand]] [[PDP-11 architecture#Operands\|modes]] used in a particular instruction, and the [[main memory]] speed (with the [[asynchronous]] QBUS), that could add up to roughly 12 μseconds to that basic time. (The extra time is roughly linear in the number of [[memory cycle]]s, at 1.4-2.1 μseconds per cycle - depending on the operand modes, PDP-11 instructions could add up to 6 additional memory cycles per instruction, above the 1 needed to [[fetch]] the basic instruction.)		The basic [[clock]] μcycle is 350 nsec; simple [[register]]-register [[instruction]]s (e.g. MOV, ADD) took 3.5 μseconds; depending on the exact [[operand]] [[PDP-11 architecture#Operands\|modes]] used in a particular instruction, and the [[main memory]] speed (with the [[asynchronous]] QBUS), that could add up to roughly 12 μseconds to that basic time. (The extra time is roughly linear in the number of [[memory cycle]]s, at 1.4-2.1 μseconds per cycle - depending on the operand modes, PDP-11 instructions could add up to 6 additional memory cycles per instruction, above the 1 needed to [[fetch]] the basic instruction.)

← Older revision		Revision as of 15:30, 7 December 2021
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	* [[KDF11 CPUs]]		* [[KDF11 CPUs]]
		+
		+	==External links==
		+
		+	* Mark J. Sebern, [http://gordonbell.azurewebsites.net/Computer_Engineering/00000323.htm A Minicomputer-Compatible Microcomputer System: The DEC LSI-11], in C. Gordon Bell, J. Craig Mudge, John. E. McNamara, ''Computer Engineering: A DEC View of Hardware Systems Design'', Digital Press, Bedford, 1978

	{{PDP-11s}}		{{PDP-11s}}

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 The '''LSI-11 CPUs''' were DEC's first cost-reduced [[PDP-11]] [[Central Processing Unit|CPUs]], using a [[microprocessor]] (the [[LSI-11 chip set]]). They also used a new [[bus]], the [[QBUS]].
 They were the first PDP-11 models to not have a [[front panel]] to control them; instead, as a cost-reduction measure, the main [[asynchronous serial line|serial line]] is used as a operating console, using the [[QBUS CPU ODT|ODT functionality]].
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 They also supported the optional [[KUV11 Writeable Control Store]].
 {{PDP-11s}}

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 ==Limitations==
-Note that ODT will not function correctly in the LSI-11s unless there is [[main memory]] on the [[QBUS]]. The reason for this restriction is unknown: the [[KDF11 CPUs]] and [[KDJ11 CPUs]], which also use ODT, do not have this limitation; e.g. a system consisting only of a [[KDF11-A CPU]] and a serial console will run ODT.
+Note that ODT will not function correctly in the LSI-11s unless there is [[main memory]] on the [[QBUS]] (at location 0). The reason for this restriction is unknown: the [[KDF11 CPUs]] and [[KDJ11 CPUs]], which also use ODT, do not have this limitation; e.g. a system consisting only of a [[KDF11-A CPU]] and a serial console will run ODT.
-Both LSI-11s are [[QBUS#Variable address size|Q16]] devices; they only drive 16 address lines. Although they can be plugged into a Q18 or Q22 [[backplane]], they will '''only''' function with Q16 [[main memory]]. (With Q22 memory, the pins used for BDAL18-21 are used for other, internal signals by the LSI-11. The reason for the incompatability with Q18 memory is currently unknown.)
+Both LSI-11s are [[QBUS#Variable address size|Q16]] devices; they only drive 16 address lines. Although they can be plugged into a Q18 or Q22 [[backplane]], they will '''only''' function with Q16 or Q18 [[main memory]]. (With Q22 memory, the pins used for BDAL18-21 are used for other, internal signals by the LSI-11.<!--The reason for the incompatability with Q18 memory is currently unknown.-->)
 ==Options==