LSI-11 chip set - Revision history

Jnc: Grammar error

2026-10-11T06:23:51Z

Grammar error

← Older revision		Revision as of 06:23, 11 October 2026
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	===Internal details===		===Internal details===

	The data path chip includes a [[register file]] and the [[Arithmetic logic unit\|ALU]]; all are 8 bits wide (so PDP-11 word operations two [[microcycle]]s). The register file contains 26 entries (paired into 16-bit composites).		The data path chip includes a [[register file]] and the [[Arithmetic logic unit\|ALU]]; all are 8 bits wide (so PDP-11 word operations take two [[microcycle]]s). The register file contains 26 entries (paired into 16-bit composites).

	5 pairs are directly addressable from the microcode, 6 pairs an only be addressed indirectly (via a 3-bit internal register, loadable from the [[PDP-11 architecture#Operands\|register fields]] ), and 2 pairs support both:		5 pairs are directly addressable from the microcode, 6 pairs an only be addressed indirectly (via a 3-bit internal register, loadable from the [[PDP-11 architecture#Operands\|register fields]] ), and 2 pairs support both:

Jnc: /* External links */ original at Frain Research went offline; add reference to online mirror

2025-05-31T12:42:48Z

External links: original at Frain Research went offline; add reference to online mirror

← Older revision		Revision as of 12:42, 31 May 2025
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	* [http://www.bitsavers.org/pdf/dec/pdp11/1103/Titelbaum_LSI-11_1975.pdf The LSI-11 - A System Microcomputer]		* [http://www.bitsavers.org/pdf/dec/pdp11/1103/Titelbaum_LSI-11_1975.pdf The LSI-11 - A System Microcomputer]
	* [http://www.bitsavers.org/pdf/dec/pdp11/1103/EK-LSI11-TM-002.pdf LSI-11, PDP-11/03 user's manual] (EK-LSI11-TM-002)		* [http://www.bitsavers.org/pdf/dec/pdp11/1103/EK-LSI11-TM-002.pdf LSI-11, PDP-11/03 user's manual] (EK-LSI11-TM-002)
	* [http://web.frainresearch.org:8080/projects/pdp-11/lsi-11.php LSI-11 Processors]		* [http://web.frainresearch.org:8080/projects/pdp-11/lsi-11.php LSI-11 Processors] (mirrored [https://electrickery.nl/comp/pdp11_23plus/frain.rsx11m.io/lsi-11.php here])
	* [https://github.com/brouhaha/cp16dis Microcode disassembler]		* [https://github.com/brouhaha/cp16dis Microcode disassembler]
	* [https://en.wikichip.org/wiki/dec/lsi-11 WikiChip LSI-11]		* [https://en.wikichip.org/wiki/dec/lsi-11 WikiChip LSI-11]

Jnc: /* Further reading */ +Extended Memory for the LSI-11

2024-07-27T17:21:37Z

Further reading: +Extended Memory for the LSI-11

← Older revision		Revision as of 17:21, 27 July 2024
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	The 3010D contains uROM addresses 0x000-0x1ff, and the 3007D 23-002B5 contains 0x200-0x3ff.		The 3010D contains uROM addresses 0x000-0x1ff, and the 3007D 23-002B5 contains 0x200-0x3ff.

			==Further reading==

			* ''Extended Memory for the LSI-11'', [[MicroNote]] #028

	==External links==		==External links==

Jnc: /* External links */ +CPU of the Day: DEC LSI-11 Chipset

2023-12-20T20:42:36Z

External links: +CPU of the Day: DEC LSI-11 Chipset

← Older revision		Revision as of 20:42, 20 December 2023
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	* [https://github.com/brouhaha/cp16dis Microcode disassembler]		* [https://github.com/brouhaha/cp16dis Microcode disassembler]
	* [https://en.wikichip.org/wiki/dec/lsi-11 WikiChip LSI-11]		* [https://en.wikichip.org/wiki/dec/lsi-11 WikiChip LSI-11]
			* [https://www.cpushack.com/2017/11/22/cpu-of-the-day-dec-lsi-11-chipset/ CPU of the Day: DEC LSI-11 Chipset]
	* [http://www.brouhaha.com/~eric/retrocomputing/wd/microengine/microcode/ Western Digital WD9000 Pascal Microengine Microcode]		* [http://www.brouhaha.com/~eric/retrocomputing/wd/microengine/microcode/ Western Digital WD9000 Pascal Microengine Microcode]

Jnc: /* External links */ +several more good ones

2023-07-08T05:19:04Z

External links: +several more good ones

← Older revision		Revision as of 05:19, 8 July 2023
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	* Mark J. Sebern, [http://gordonbell.azurewebsites.net/Computer_Engineering/00000125.htm A Minicomputer-Compatible Microcomputer System: The DEC LSI-11], in C. Gordon Bell, J. Craig Mudge, John. E. McNamara, ''Computer Engineering: A DEC View of Hardware Systems Design'', Digital Press, Bedford, 1978		* Mark J. Sebern, [http://gordonbell.azurewebsites.net/Computer_Engineering/00000125.htm A Minicomputer-Compatible Microcomputer System: The DEC LSI-11], in C. Gordon Bell, J. Craig Mudge, John. E. McNamara, ''Computer Engineering: A DEC View of Hardware Systems Design'', Digital Press, Bedford, 1978
			* [http://www.bitsavers.org/pdf/dec/pdp11/1103/Titelbaum_LSI-11_1975.pdf The LSI-11 - A System Microcomputer]
			* [http://www.bitsavers.org/pdf/dec/pdp11/1103/EK-LSI11-TM-002.pdf LSI-11, PDP-11/03 user's manual] (EK-LSI11-TM-002)
	* [http://web.frainresearch.org:8080/projects/pdp-11/lsi-11.php LSI-11 Processors]		* [http://web.frainresearch.org:8080/projects/pdp-11/lsi-11.php LSI-11 Processors]
	* [https://github.com/brouhaha/cp16dis Microcode disassembler]		* [https://github.com/brouhaha/cp16dis Microcode disassembler]

Jnc: /* Internal details */ +links

2022-11-05T03:31:16Z

Internal details: +links

← Older revision		Revision as of 03:31, 5 November 2022
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	===Internal details===		===Internal details===

	The data path chip includes a register file and the [[Arithmetic logic unit\|ALU]]; all are 8 bits wide (so PDP-11 word operations two ~~microcycles~~). The register file contains 26 entries (paired into 16-bit composites).		The data path chip includes a [[register file]] and the [[Arithmetic logic unit\|ALU]]; all are 8 bits wide (so PDP-11 word operations two [[microcycle]]s). The register file contains 26 entries (paired into 16-bit composites).

	5 pairs are directly addressable from the microcode, 6 pairs an only be addressed indirectly (via a 3-bit internal register, loadable from the [[PDP-11 architecture#Operands\|register fields]] ), and 2 pairs support both:		5 pairs are directly addressable from the microcode, 6 pairs an only be addressed indirectly (via a 3-bit internal register, loadable from the [[PDP-11 architecture#Operands\|register fields]] ), and 2 pairs support both:

Jnc: /* External links */ +Frain link

2022-10-28T16:47:36Z

External links: +Frain link

← Older revision		Revision as of 16:47, 28 October 2022
Line 75:		Line 75:

	* Mark J. Sebern, [http://gordonbell.azurewebsites.net/Computer_Engineering/00000125.htm A Minicomputer-Compatible Microcomputer System: The DEC LSI-11], in C. Gordon Bell, J. Craig Mudge, John. E. McNamara, ''Computer Engineering: A DEC View of Hardware Systems Design'', Digital Press, Bedford, 1978		* Mark J. Sebern, [http://gordonbell.azurewebsites.net/Computer_Engineering/00000125.htm A Minicomputer-Compatible Microcomputer System: The DEC LSI-11], in C. Gordon Bell, J. Craig Mudge, John. E. McNamara, ''Computer Engineering: A DEC View of Hardware Systems Design'', Digital Press, Bedford, 1978
			* [http://web.frainresearch.org:8080/projects/pdp-11/lsi-11.php LSI-11 Processors]
	* [https://github.com/brouhaha/cp16dis Microcode disassembler]		* [https://github.com/brouhaha/cp16dis Microcode disassembler]
	* [https://en.wikichip.org/wiki/dec/lsi-11 WikiChip LSI-11]		* [https://en.wikichip.org/wiki/dec/lsi-11 WikiChip LSI-11]

Jnc: /* Internal details */ Have pages now

2021-12-10T16:56:26Z

Internal details: Have pages now

← Older revision		Revision as of 16:56, 10 December 2021
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	\| 16-17 \|\| x \|\| x \|\| R7 ([[Program Counter\|PC]])		\| 16-17 \|\| x \|\| x \|\| R7 ([[Program Counter\|PC]])
	\|-		\|-
	\| 20-21 \|\| x \|\|   \|\| [[IR]]		\| 20-21 \|\| x \|\|   \|\| [[Instruction Register\|IR]]
	\|-		\|-
	\| 22-23 \|\| x \|\|   \|\| [[BA]]		\| 22-23 \|\| x \|\|   \|\| [[Bus Address Register\|BAR]]
	\|-		\|-
	\| 24-25 \|\| x \|\|   \|\| Source		\| 24-25 \|\| x \|\|   \|\| Source

Jnc: Internal details, link to relevant chapter in 'Computer Engineering'

2021-12-10T16:38:35Z

Internal details, link to relevant chapter in 'Computer Engineering'

@@ Line 5: / Line 5: @@
 ==Chips==
-The chip set consists of a [[data path]] chip, a control chip, and two or three [[microcode]] [[Read-only memory|ROMs]] (each holding 512 words which are 22 bits wide). (The microcode is thus more 'vertical' than 'horizontal'.)
+The chip set consists of a [[data path]] chip, a control chip, and two or three [[microcode]] [[Read-only memory|ROMs]] (each holding 512 microwords, which are 22 bits wide). (The microcode is thus more 'vertical' than 'horizontal'.)
-The data path chip contains data paths, [[register]]s, and logic to perform [[micro-instruction]]s; it includes a register file, the [[Arithmetic logic unit|ALU]], [[condition codes]] logic, and a data port which gives access to the [[QBUS]]' data/[[address]] lines.
+The data path chip contains data paths, [[register]]s, and logic to perform [[micro-instruction]]s. The control chip contains micro-instruction sequencing, and control for the QBUS.
-The control chip contains micro-instruction sequencing, and control for the data port; it includes a 'programmable translation array', which decodes [[macro-instruction]]s to produce microcode [[address]]es, the 'location counter' (micro-[[program counter]]), the 'return register' (microcode [[subroutine]] return), and [[interrupt]] logic.
+The uROMs all have the same pinout, and are wired in parallel, so they can be placed in any of the three uROM positions. The first two uROMs contain the basic [[PDP-11]] [[instruction set]]; the third uROM is optional, and a number of different choices are available.
-The uROMs all have the same pinout, and are wired in parallel, so they can be placed in any of the three uROM positions. The first two uROMs contain the basic [[PDP-11]] [[instruction set]]; the third uROM is optional, and a number of different choices are available.
+===Internal details===
-One is the [[KEV11-A floating point|KEV11-A]], for the [[PDP-11 Extended Instruction Set|EIS]]/[[FIS floating point|FIS]] instructions; the [[KEV11-B Extended Instruction Set|KEV11-B]] provides EIS without FIS; the [[KEV11-C Commercial Instruction Set‎|KEV11-C]] provides a subset of the PDP-11 [[PDP-11 Commercial Instruction Set|CIS]] (it also apparently includes the EIS, but not the FIS).
+The chip also contains [[condition codes]] logic, and a data port which gives access to the [[QBUS]]' data/[[address]] lines.
-Some verions of the CPU boards also support the optional [[KUV11 Writeable Control Store]].
+The control chip contains control for the data port; it includes a 'programmable translation array', which decodes [[macro-instruction]]s to produce microcode [[address]]es, the 11-bit 'location counter' (micro-program counter), the 'return register' (microcode [[subroutine]] return), and [[interrupt]] logic.
 ==Chip variants==
@@ Line 36: / Line 74: @@
 ==External links==
 * [https://github.com/brouhaha/cp16dis Microcode disassembler]
 * [https://en.wikichip.org/wiki/dec/lsi-11 WikiChip LSI-11]

Jnc: chips don't have a bus

2021-11-19T20:45:47Z

chips don't have a bus

← Older revision		Revision as of 20:45, 19 November 2021
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	[[Category: PDP-11 Processors]]		[[Category: PDP-11 Processors]]
	~~[[Category: QBUS Processors]]~~