Load-store architecture - Revision history

Jnc: typo

2019-11-22T22:36:25Z

typo

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	Early computers often had load-store architectures because that approach resulted in simple instruction sets (especially on computers which had only an [[accumulator]]), and thus simple implementations. (The [[PDP-8]] is a machine which went this direction.)		Early computers often had load-store architectures because that approach resulted in simple instruction sets (especially on computers which had only an [[accumulator]]), and thus simple implementations. (The [[PDP-8]] is a machine which went this direction.)

	More recently, [[Reduced Instruction Set Computer\|RISC]] computers often were of this type; the single memory operation per instruction led to simple instructions, which allowed the machine's cycle time to be kept low, a key goal of RISC machines. Also, because all instructions had at most one memory address, it made it easy to have fixed-length ~~instuctions~~, which made constructing [[pipeline]]s easier (since an instruction did not have to be partially decoded to tell how long it was, i.e. where the next instruction started).		More recently, [[Reduced Instruction Set Computer\|RISC]] computers often were of this type; the single memory operation per instruction led to simple instructions, which allowed the machine's cycle time to be kept low, a key goal of RISC machines. Also, because all instructions had at most one memory address, it made it easy to have fixed-length instructions, which made constructing [[pipeline]]s easier (since an instruction did not have to be partially decoded to tell how long it was, i.e. where the next instruction started).

	[[Complex Instruction Set Computer\|CISC]] computers were usually not load-store, as they often had instructions in which both the source and destination were in main memory. The [[object code]] can be denser (since instructions can do more), which was important in the [[core memory]] era, when main memory was very expensive.		[[Complex Instruction Set Computer\|CISC]] computers were usually not load-store, as they often had instructions in which both the source and destination were in main memory. The [[object code]] can be denser (since instructions can do more), which was important in the [[core memory]] era, when main memory was very expensive.

	[[Category: Computer Basics]]		[[Category: Computer Basics]]

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2019-11-22T22:35:36Z

code density

← Older revision		Revision as of 22:35, 22 November 2019
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	More recently, [[Reduced Instruction Set Computer\|RISC]] computers often were of this type; the single memory operation per instruction led to simple instructions, which allowed the machine's cycle time to be kept low, a key goal of RISC machines. Also, because all instructions had at most one memory address, it made it easy to have fixed-length instuctions, which made constructing [[pipeline]]s easier (since an instruction did not have to be partially decoded to tell how long it was, i.e. where the next instruction started).		More recently, [[Reduced Instruction Set Computer\|RISC]] computers often were of this type; the single memory operation per instruction led to simple instructions, which allowed the machine's cycle time to be kept low, a key goal of RISC machines. Also, because all instructions had at most one memory address, it made it easy to have fixed-length instuctions, which made constructing [[pipeline]]s easier (since an instruction did not have to be partially decoded to tell how long it was, i.e. where the next instruction started).

	[[Complex Instruction Set Computer\|CISC]] computers were usually not load-store, as they often had instructions in which both the source and destination were in main memory.		[[Complex Instruction Set Computer\|CISC]] computers were usually not load-store, as they often had instructions in which both the source and destination were in main memory. The [[object code]] can be denser (since instructions can do more), which was important in the [[core memory]] era, when main memory was very expensive.

	[[Category: Computer Basics]]'		[[Category: Computer Basics]]

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2018-12-16T00:01:03Z

+cat

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	[[Complex Instruction Set Computer\|CISC]] computers were usually not load-store, as they often had instructions in which both the source and destination were in main memory.		[[Complex Instruction Set Computer\|CISC]] computers were usually not load-store, as they often had instructions in which both the source and destination were in main memory.

			[[Category: Computer Basics]]'

Jnc: An OK start

2017-09-30T19:15:54Z

An OK start

New page

A '''load-store architecture''' for a [[Central Processing Unit|CPU]] is one in which [[instruction]]s which reference [[main memory]] are limited to a single operation to that memory - either a load, or a store (hence the name).

Early computers often had load-store architectures because that approach resulted in simple instruction sets (especially on computers which had only an [[accumulator]]), and thus simple implementations. (The [[PDP-8]] is a machine which went this direction.)

More recently, [[Reduced Instruction Set Computer|RISC]] computers often were of this type; the single memory operation per instruction led to simple instructions, which allowed the machine's cycle time to be kept low, a key goal of RISC machines. Also, because all instructions had at most one memory address, it made it easy to have fixed-length instuctions, which made constructing [[pipeline]]s easier (since an instruction did not have to be partially decoded to tell how long it was, i.e. where the next instruction started).

[[Complex Instruction Set Computer|CISC]] computers were usually not load-store, as they often had instructions in which both the source and destination were in main memory.