M7259 Parity Control Module - Revision history

Jnc: /* See also */ +M7850 parity controller

2022-07-06T20:21:56Z

‎See also: +M7850 parity controller

Jnc: typo

2022-04-09T13:11:14Z

typo

Jnc: +imgs

2022-04-04T16:39:16Z

+imgs

Jnc: Describe implementation

2022-04-04T11:03:58Z

Describe implementation

Jnc: A good start

2022-04-04T02:28:09Z

A good start

New page

The '''M7259 Parity Control Module''' is an optional accessory for the [[parity]] versions of the [[MM11-L core memory|MM11-L]] and [[MM11-U core memory]] [[main memory]] systems on the [[UNIBUS]]; it is needed for them to actually provide the parity protection.

It provides byte parity. Memory [[access time]] on read is increased by 125 nsec if parity is enabled. [[Cycle time]] on write is not affected if parity is enabled. On later revisions of the M7259, if an error occurs, an [[Light Emitting Diode|LED]] on the end is illuminated.

The M7259 is a [[DEC card form factor|dual]] format card, which plus into a dedicated slot of the MF11-L/MM11-U backplane into which the associated memory unit(s) are plugged. Parity, and the M7259, is thus not supported for MM11-L/MM11-U units in a [[PDP-11/05]] [[Central Processing Unit|CPU]] backplane.

The M7259 requires slightly different [[backplane]] wiring for parity memory from non-parity. One M7850 can provide parity support to as many memory units as the backplane holds (3 for the MM11-L; 2 for the MM11-U).

==Control and Status Register==

The M7259 has a single [[register]] to control and monitor its operation. Its [[address]] may be set in the range 0772100-0772136 by a group of [[jumper]]s on the M7259. Its format is:
{{16bit-header}}
| ParErr || colspan=3 | Unused || colspan=7 | ErrAddr || colspan=2 | Unused || WrWrong || Unused || SignalErr
{{16bitoctal-bitout}}

Errors are not signaled to the CPU unless bit 0 is set. After an error, the ErrAddr field contains the highest-order address bits (A17-A11) of the location which produced the error. All bits can be written by the CPU; all except the Error Address are cleared by the INIT bus [[signal]].

==See also==

* [[UNIBUS parity]]

==External links==

* [http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-11-HMFLA-C-D%20MM11-S,%20MF11-L,%20and%20MF11-LP%20core%20memory%20systems.pdf MM11-S, MF11-L, and MF11-LP core memory systems] (DEC-11-HMFLA-C-D) - the M7259 is covered in Appendix A
* [http://www.bitsavers.org/pdf/dec/pdp11/memory/MF11-U_UP_Memory_System_Engineering_Drawings_RevF_Jan76.pdf MF11-U/UP memory system engineering drawings] - the M7259 is covered on pp. 7-40 of the PDF

[[Category: UNIBUS Memories]]

@@ Line 32: / Line 32: @@
 <!-- ==See also==
 -->
 ==External links==

@@ Line 7: / Line 7: @@
 The M7259 is a [[DEC card form factor|dual]] format card, which plus into a dedicated slot of the MF11-L/MM11-U/MM11-W backplane into which the associated memory unit(s) are plugged. Parity, and the M7259, is thus not supported for MM11-L/MM11-U units in a [[PDP-11/05]] [[Central Processing Unit|CPU]] backplane.
-The M7259 requires slightly different [[backplane]] wiring for parity memory from non-parity (below). One M7850 can provide parity support to as many memory units as the backplane holds (3 for the MM11-L; 2 for the MM11-U).
+The M7259 requires slightly different [[backplane]] wiring for parity memory from non-parity (below). One M7259 can provide parity support to as many memory units as the backplane holds (3 for the MM11-L; 2 for the MM11-U).
 ==Operation==

@@ Line 1: / Line 1: @@
-<!-- [[Image:M7259ParityControlModule.jpg|250px|thumb|right|M7259 Parity Module]]
+[[Image:M7259ParityControlOld.jpg|200px|thumb|right|M7259 Parity Module, old version]]
--->
 The '''M7259 Parity Control Module''' is an optional accessory for the [[parity]] versions of the [[MM11-L core memory|MM11-L]], [[MM11-U core memory|MM11-U]] and [[MM11-W core memory]] [[main memory]] systems on the [[UNIBUS]]; it is needed for them to actually provide the parity protection.
@@ Line 10: / Line 10: @@
 ==Operation==
 The way the M7259 works is the same in all three memory systems that support it. An 'internal' version of the UNIBUS SSYN [[signal]], SSYN INT BUS L, on [[DEC edge connector contact identification|pin]] BU1, connects together all memory units in the backplane, and the M7259.

@@ Line 1: / Line 1: @@
 <!-- [[Image:M7259ParityControlModule.jpg|250px|thumb|right|M7259 Parity Module]]
 -->
-The '''M7259 Parity Control Module''' is an optional accessory for the [[parity]] versions of the [[MM11-L core memory|MM11-L]] and [[MM11-U core memory]] [[main memory]] systems on the [[UNIBUS]]; it is needed for them to actually provide the parity protection.
+The '''M7259 Parity Control Module''' is an optional accessory for the [[parity]] versions of the [[MM11-L core memory|MM11-L]], [[MM11-U core memory|MM11-U]] and [[MM11-W core memory]] [[main memory]] systems on the [[UNIBUS]]; it is needed for them to actually provide the parity protection.
-It provides byte parity. Memory [[access time]] on read is increased by 125 nsec if parity is enabled.<!-- if there is no error, and by 200 nsec if there is --> [[Cycle time]] on write is not affected if parity is enabled.<!-- increased by 40 nsec. --> On later revisions of the M7259, if an error occurs, an [[Light Emitting Diode|LED]] on the end is illuminated.
+It provides byte parity. Memory [[access time]] on read is increased by 125 nsec if parity is enabled.<!-- if there is no error, and by 200 nsec if there is --> [[Cycle time]] on write is not affected if parity is enabled.<!-- increased by 40 nsec. --> On later revisions of the M7259, if an error occurs, an [[Light Emitting Diode|LED]] is illuminated.
-The M7259 is a [[DEC card form factor|dual]] format card, which plus into a dedicated slot of the MF11-L/MM11-U backplane into which the associated memory unit(s) are plugged. Parity, and the M7259, is thus not supported for MM11-L/MM11-U units in a [[PDP-11/05]] [[Central Processing Unit|CPU]] backplane.
+The M7259 is a [[DEC card form factor|dual]] format card, which plus into a dedicated slot of the MF11-L/MM11-U/MM11-W backplane into which the associated memory unit(s) are plugged. Parity, and the M7259, is thus not supported for MM11-L/MM11-U units in a [[PDP-11/05]] [[Central Processing Unit|CPU]] backplane.
-The M7259 requires slightly different [[backplane]] wiring for parity memory from non-parity. One M7850 can provide parity support to as many memory units as the backplane holds (3 for the MM11-L; 2 for the MM11-U).
+The M7259 requires slightly different [[backplane]] wiring for parity memory from non-parity (below). One M7850 can provide parity support to as many memory units as the backplane holds (3 for the MM11-L; 2 for the MM11-U).
 ==Control and Status Register==
-The M7259 has a single [[register]] to control and monitor its operation. Its [[address]] may be set in the range 0772100-0772136 by a group of [[jumper]]s on the M7259. Its format is:
+The M7259 has a single [[register]] to control and monitor its operation. Its [[address]] may be set in the range 0772100-0772136 by a group of jumpers on the M7259. Its format is:
 {{16bit-header}}
 | ParErr || colspan=3 | Unused || colspan=7 | ErrAddr || colspan=2 | Unused || WrWrong || Unused || SignalErr
 {{16bitoctal-bitout}}
-Errors are not signaled to the CPU unless bit 0 is set. After an error, the ErrAddr field contains the highest-order address bits (A17-A11) of the location which produced the error. All bits can be written by the CPU; all except the Error Address are cleared by the INIT bus [[signal]].
+Errors are not signaled to the CPU unless bit 0 is set. After an error, the ErrAddr field contains the highest-order address bits (A17-A11) of the location which produced the error. All bits can be written by the CPU; all except the Error Address are cleared by the INIT UNIBUS signal.
 ==External links==