M7850 parity controller - Revision history

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2024-04-19T22:07:21Z

typo

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‎See also: +M7259 Parity Control Module

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The '''M7850 parity controller''' is an optional accessory for mid-period [[main memory]] on the [[UNIBUS]]; it provides byte [[parity]] for memory units (such as the [[MM11-D core memory‎]] and [[MS11 32KB MOS memory]]) which i) provide the two extra [[bit]]s of memory per [[PDP-11]] [[word]] needed to hold the parity, and ii) are set up to interact with the M7850. It works with both [[core memory]] and [[Metal Oxide Semiconductor|MOS]] [[Dynamic RAM|DRAM]] memory.

The M7850 is a [[DEC card form factor|dual]] format card, which plus into the [[DEC edge connector contact identification|two top (AB) sections]] of the [[Modified UNIBUS Device|MUD]] [[backplane]] into which the associated memory unit(s) are plugged. One M7850 can provide parity support to as many memory units as the backplane holds.

==See also==

* [[UNIBUS parity]]

==External links==

* [http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/EK-M7850-MM-001%20M7850%20Parity%20Controller%20Maintenance%20Manual.pdf M7850 parity controller maintenance manual] (EK-M7850-MM-001)
* [http://www.bitsavers.org/pdf/dec/pdp11/1134/MP00082_1134_Vol2_Sep76.pdf 11/34 Vol. 2 Field Maintenance Print Set] - the M7850 is covered on pp. 93-95 of the PDF

[[Category: UNIBUS Memories]]

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 Unlike the earlier [[M7259 Parity Control Module]], which has different backplane wiring for parity and non-parity memory, no hardware changes are needed to switch from non-parity to parity memory with the M7850. When the M7850 is inserted in a [[backplane]] which also holds parity-capable (as above) memory, the latter detects the presence of the M7850 and alters its operation to function with the M7850 to provide parity checking.
-The M7850 is a [[DEC card form factor|dual]] format card, which plus into the [[DEC edge connector contact identification|two top (AB) sections]] of the [[Modified UNIBUS Device|MUD]] backplane into which the associated memory unit(s) are plugged. (Since all the relevant memory modules are hex-sized, the M7850 must go in another slot.) One M7850 can provide parity support to as many memory units as the backplane holds.
+The M7850 is a [[DEC card form factor|dual]] format card, which plugs into the [[DEC edge connector contact identification|two top (AB) sections]] of the [[Modified UNIBUS Device|MUD]] backplane into which the associated memory unit(s) are plugged. (Since all the relevant memory modules are hex-sized, the M7850 must go in another slot.) One M7850 can provide parity support to as many memory units as the backplane holds.
 ==Control and Status Register==

← Older revision		Revision as of 20:19, 6 July 2022
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	==See also==		==See also==

		+	* [[M7259 Parity Control Module]]
	* [[UNIBUS parity]]		* [[UNIBUS parity]]

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-<!-- [[Image:M7850ParityController.jpg|250px|thumb|right|M7850 parity controller]]
+[[Image:M7850ParityController.jpg|250px|thumb|right|M7850 parity controller]]
-The M7850 is a [[DEC card form factor|dual]] format card, which plus into the [[DEC edge connector contact identification|two top (AB) sections]] of the [[Modified UNIBUS Device|MUD]] [[backplane]] into which the associated memory unit(s) are plugged. One M7850 can provide parity support to as many memory units as the backplane holds.
+The '''M7850 parity controller''' is an optional accessory for mid-period [[main memory]] on the [[UNIBUS]];  it provides byte [[parity]] for memory units (such as the [[MM11-D core memory‎]] and [[MS11 32KB MOS memory]]) which i) provide the two extra [[bit]]s of memory per [[PDP-11]] [[word]] needed to hold the parity, and ii) are set up to interact with the M7850. It works with both [[core memory]] and [[Metal Oxide Semiconductor|MOS]] [[Dynamic RAM|DRAM]] memory.
 ==See also==