MA10 core memory - Revision history

Jnc: interleaving cleanup

2023-08-02T11:53:23Z

interleaving cleanup

Jnc: cat caps

2022-04-23T11:20:20Z

cat caps

Jnc: /* External links */ +Manual

2021-10-17T21:04:44Z

‎External links: +Manual

Jnc: +parity, access time

2019-03-11T14:22:42Z

+parity, access time

Jnc: +core

2019-03-07T02:32:34Z

+core

Jnc: + port disable

2019-03-07T02:12:15Z

+ port disable

Jnc: +addr

2019-03-06T02:14:50Z

+addr

Jnc: The basics

2019-03-06T00:14:19Z

The basics

New page

The '''MA-10''' was a [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MA10 contained 16KW, and had a [[cycle time]] of 1.0 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.

It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.

Each port could be independently set for [[interleaving]], using [[address]] bits 21 and 35.

[[Category: PDP-10 memories]]

@@ Line 3: / Line 3: @@
 It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
-Each port could be independently set for its address, to disable the low or high 8KW, and for [[interleaving]] (using [[address]] bits 21 and 35).
+Each port could be independently set for its address, to disable the low or high 8KW, and for [[memory interleaving|interleaving]] (using [[address]] bits 21 and 35).
 ==External links==

← Older revision		Revision as of 11:20, 23 April 2022
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	* [http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-10-HIAA-D%20MA10%20Core%20Memory%20Maintenance%20Manual.pdf MA10 Core Memory Maintenance Manual] (DEC-10-HIAA-D)		* [http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-10-HIAA-D%20MA10%20Core%20Memory%20Maintenance%20Manual.pdf MA10 Core Memory Maintenance Manual] (DEC-10-HIAA-D)

−	[[Category: PDP-10 ~~memories~~]]	+	[[Category: PDP-10 Memories]]

← Older revision		Revision as of 21:04, 17 October 2021
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	Each port could be independently set for its address, to disable the low or high 8KW, and for [[interleaving]] (using [[address]] bits 21 and 35).		Each port could be independently set for its address, to disable the low or high 8KW, and for [[interleaving]] (using [[address]] bits 21 and 35).
		+
		+	==External links==
		+
		+	* [http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-10-HIAA-D%20MA10%20Core%20Memory%20Maintenance%20Manual.pdf MA10 Core Memory Maintenance Manual] (DEC-10-HIAA-D)

	[[Category: PDP-10 memories]]		[[Category: PDP-10 memories]]

← Older revision		Revision as of 14:22, 11 March 2019
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−	The '''MA10''' was a [[core memory\|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MA10 contained 16KW, and ~~had~~ a [[cycle time]] of 1.0 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.	+	The '''MA10''' was a [[core memory\|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MA10 contained 16KW; [[parity]] was provided to protect the memory contents. It had an [[access time]] of 0.55 μseconds, and a [[cycle time]] of .93 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.

	It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

← Older revision		Revision as of 02:32, 7 March 2019
Line 1:		Line 1:
−	The '''MA10''' was a [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MA10 contained 16KW, and had a [[cycle time]] of 1.0 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.	+	The '''MA10''' was a [[core memory\|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MA10 contained 16KW, and had a [[cycle time]] of 1.0 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.

	It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

@@ Line 1: / Line 1: @@
-The '''MA-10''' was a [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MA10 contained 16KW, and had a [[cycle time]] of 1.0 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.
+The '''MA10''' was a [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MA10 contained 16KW, and had a [[cycle time]] of 1.0 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.
-It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by  [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
+It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
-Each port could be independently set for its address, and for [[interleaving]] (using [[address]] bits 21 and 35).
+Each port could be independently set for its address, to disable the low or high 8KW, and for [[interleaving]] (using [[address]] bits 21 and 35).
 [[Category: PDP-10 memories]]