MA20 core memory - Revision history

Jnc: interleaving cleanup

2023-08-01T02:17:13Z

interleaving cleanup

← Older revision		Revision as of 02:17, 1 August 2023
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	The '''MA20''' was a [[core memory\|core]] [[main memory]] system for the later [[PDP-10]]s, principally the mid-period [[KL10]]; it connected to the KL10's so-called internal memory bus, the [[PDP-10 Memory Bus\|S-Bus]]. An MA20 contained two memory controllers (numbered 0 and 1, or 2 and 3), each with up to four 16KW storage modules, for a maximum of 128KW; [[parity]] is provided to protect the memory contents. The [[access time]] is 1.00 µseconds, and the [[cycle time]] is 1.92 µseconds (both for the first [[word]] in a 4-word block, using four-way [[interleaving]]).		The '''MA20''' was a [[core memory\|core]] [[main memory]] system for the later [[PDP-10]]s, principally the mid-period [[KL10]]; it connected to the KL10's so-called internal memory bus, the [[PDP-10 Memory Bus\|S-Bus]]. An MA20 contained two memory controllers (numbered 0 and 1, or 2 and 3), each with up to four 16KW storage modules, for a maximum of 128KW; [[parity]] is provided to protect the memory contents. The [[access time]] is 1.00 µseconds, and the [[cycle time]] is 1.92 µseconds (both for the first [[word]] in a 4-word block, using four-way [[memory interleaving\|interleaving]]).

	Controllers 0 and 1 are connected to S-Bus 0, and controllers 2 and 3 to S-Bus 1. For interleaving, each controller is configured as to which addresses (out of the 4 in an S-Bus block) it will respond to; both 2-way and 4-way interleaving require controllers to be set to 'odd' or 'even'. In 4-way interleaving, in addition to two controllers being actuated at the same time, each controller can start two modules reading at the same time.		Controllers 0 and 1 are connected to S-Bus 0, and controllers 2 and 3 to S-Bus 1. For interleaving, each controller is configured as to which addresses (out of the 4 in an S-Bus block) it will respond to; both 2-way and 4-way interleaving require controllers to be set to 'odd' or 'even'. In 4-way interleaving, in addition to two controllers being actuated at the same time, each controller can start two modules reading at the same time.

Jnc: +link

2022-10-23T01:23:57Z

+link

← Older revision		Revision as of 01:23, 23 October 2022
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	The '''MA20''' was a [[core memory\|core]] [[main memory]] system for the later [[PDP-10]]s, principally the mid-period [[KL10]]; it connected to the KL10's so-called internal memory bus, the S-Bus. An MA20 contained two memory controllers (numbered 0 and 1, or 2 and 3), each with up to four 16KW storage modules, for a maximum of 128KW; [[parity]] is provided to protect the memory contents. The [[access time]] is 1.00 µseconds, and the [[cycle time]] is 1.92 µseconds (both for the first [[word]] in a 4-word block, using four-way [[interleaving]]).		The '''MA20''' was a [[core memory\|core]] [[main memory]] system for the later [[PDP-10]]s, principally the mid-period [[KL10]]; it connected to the KL10's so-called internal memory bus, the [[PDP-10 Memory Bus\|S-Bus]]. An MA20 contained two memory controllers (numbered 0 and 1, or 2 and 3), each with up to four 16KW storage modules, for a maximum of 128KW; [[parity]] is provided to protect the memory contents. The [[access time]] is 1.00 µseconds, and the [[cycle time]] is 1.92 µseconds (both for the first [[word]] in a 4-word block, using four-way [[interleaving]]).

	Controllers 0 and 1 are connected to S-Bus 0, and controllers 2 and 3 to S-Bus 1. For interleaving, each controller is configured as to which addresses (out of the 4 in an S-Bus block) it will respond to; both 2-way and 4-way interleaving require controllers to be set to 'odd' or 'even'. In 4-way interleaving, in addition to two controllers being actuated at the same time, each controller can start two modules reading at the same time.		Controllers 0 and 1 are connected to S-Bus 0, and controllers 2 and 3 to S-Bus 1. For interleaving, each controller is configured as to which addresses (out of the 4 in an S-Bus block) it will respond to; both 2-way and 4-way interleaving require controllers to be set to 'odd' or 'even'. In 4-way interleaving, in addition to two controllers being actuated at the same time, each controller can start two modules reading at the same time.

Jnc: cat caps

2022-04-22T12:45:45Z

cat caps

← Older revision		Revision as of 12:45, 22 April 2022
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	* [http://www.bitsavers.org/pdf/dec/pdp10/memory/MP00010_MA20_Schematic_Jul76.pdf MA20 Field Maintenance Print Set] (MP00010)		* [http://www.bitsavers.org/pdf/dec/pdp10/memory/MP00010_MA20_Schematic_Jul76.pdf MA20 Field Maintenance Print Set] (MP00010)

	[[Category: PDP-10 ~~memories~~]]		[[Category: PDP-10 Memories]]

Jnc: /* External links */ +FMPS

2021-10-17T10:46:06Z

External links: +FMPS

← Older revision		Revision as of 10:46, 17 October 2021
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	* [[MB20 core memory]]		* [[MB20 core memory]]

			==External links==

			* [http://www.bitsavers.org/pdf/dec/pdp10/memory/MP00010_MA20_Schematic_Jul76.pdf MA20 Field Maintenance Print Set] (MP00010)

	[[Category: PDP-10 memories]]		[[Category: PDP-10 memories]]

Jnc: /* See also */ bah, typo

2021-04-11T16:47:38Z

Jnc: /* See also */ +1; copyedit

2021-04-11T16:47:11Z

See also: +1; copyedit

← Older revision		Revision as of 16:47, 11 April 2021
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	The '''MA20''' was a [[core memory\|core]] [[main memory]] system for the later [[PDP-10]]s, principally the mid-period [[KL10]]. An MA20 contained two memory controllers (numbered 0 and 1, or 2 and 3), each with up to four 16KW storage modules, for a maximum of 128KW; [[parity]] is provided to protect the memory contents. The [[access time]] is 1.00 µseconds, and the [[cycle time]] is 1.92 µseconds (both for the first [[word]] in a 4-word block, using four-way [[interleaving]]).		The '''MA20''' was a [[core memory\|core]] [[main memory]] system for the later [[PDP-10]]s, principally the mid-period [[KL10]]; it connected to the KL10's so-called internal memory bus, the S-Bus. An MA20 contained two memory controllers (numbered 0 and 1, or 2 and 3), each with up to four 16KW storage modules, for a maximum of 128KW; [[parity]] is provided to protect the memory contents. The [[access time]] is 1.00 µseconds, and the [[cycle time]] is 1.92 µseconds (both for the first [[word]] in a 4-word block, using four-way [[interleaving]]).

	~~It connected to the KL10's so-called internal memory bus, the S-Bus; controllers~~ 0 and 1 are connected to S-Bus 0, and controllers 2 and 3 to S-Bus 1. For interleaving, each controller is configured as to which addresses (out of the 4 in an S-Bus block) it will respond to; both 2-way and 4-way interleaving require controllers to be set to 'odd' or 'even'. In 4-way interleaving, in addition to two controllers being actuated at the same time, each controller can start two modules reading at the same time.		Controllers 0 and 1 are connected to S-Bus 0, and controllers 2 and 3 to S-Bus 1. For interleaving, each controller is configured as to which addresses (out of the 4 in an S-Bus block) it will respond to; both 2-way and 4-way interleaving require controllers to be set to 'odd' or 'even'. In 4-way interleaving, in addition to two controllers being actuated at the same time, each controller can start two modules reading at the same time.

			==See also==

			* [[MB20 core memory]

	[[Category: PDP-10 memories]]		[[Category: PDP-10 memories]]

Jnc: Found a desc of this one

2021-04-11T04:07:07Z

Found a desc of this one

New page

The '''MA20''' was a [[core memory|core]] [[main memory]] system for the later [[PDP-10]]s, principally the mid-period [[KL10]]. An MA20 contained two memory controllers (numbered 0 and 1, or 2 and 3), each with up to four 16KW storage modules, for a maximum of 128KW; [[parity]] is provided to protect the memory contents. The [[access time]] is 1.00 µseconds, and the [[cycle time]] is 1.92 µseconds (both for the first [[word]] in a 4-word block, using four-way [[interleaving]]).

It connected to the KL10's so-called internal memory bus, the S-Bus; controllers 0 and 1 are connected to S-Bus 0, and controllers 2 and 3 to S-Bus 1. For interleaving, each controller is configured as to which addresses (out of the 4 in an S-Bus block) it will respond to; both 2-way and 4-way interleaving require controllers to be set to 'odd' or 'even'. In 4-way interleaving, in addition to two controllers being actuated at the same time, each controller can start two modules reading at the same time.

[[Category: PDP-10 memories]]

← Older revision		Revision as of 16:47, 11 April 2021
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	==See also==		==See also==

	* [[MB20 core memory]		* [[MB20 core memory]]

	[[Category: PDP-10 memories]]		[[Category: PDP-10 memories]]