MB10 core memory - Revision history

Jnc: interleaving cleanup

2023-08-02T11:53:45Z

interleaving cleanup

Jnc: +link

2022-10-24T15:08:34Z

+link

Jnc: cat caps

2022-04-23T11:21:28Z

cat caps

Jnc: typo

2021-01-10T12:21:52Z

typo

Jnc: indic panel shows it had parity

2020-04-18T22:10:23Z

indic panel shows it had parity

Jnc: +access time

2019-03-12T13:07:23Z

+access time

Jnc: +core

2019-03-07T02:33:54Z

+core

Jnc: + port disable

2019-03-07T02:15:29Z

+ port disable

Jnc: +addr

2019-03-06T02:17:51Z

+addr

Jnc: The basics

2019-03-06T00:20:11Z

The basics

New page

The '''MB-10''' was a [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MB10 contained 16KW, and had a [[cycle time]] of 1.65 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.

It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.

Each port could be independently set for two-way [[interleaving]], using [[address]] bits 21 and 35.

[[Category: PDP-10 memories]]

@@ Line 3: / Line 3: @@
 It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by  [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
-Each port could be independently set for its address, and for two-way [[interleaving]] (using [[address]] bits 21 and 35).
+Each port could be independently set for its address, and for two-way [[memory interleaving|interleaving]] (using [[address]] bits 21 and 35).
 [[Category: PDP-10 Memories]]

← Older revision		Revision as of 15:08, 24 October 2022
Line 1:		Line 1:
−	The '''MB10''' was a [[core memory\|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MB10 contained 16KW; [[parity]] was provided to protect the memory contents. It had an [[access time]] of 0.60 μseconds, and a [[cycle time]] of 1.65 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.	+	The '''MB10''' was a [[core memory\|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MB10 contained 16KW; [[parity]] was provided to protect the memory contents. It had an [[access time]] of 0.60 μseconds, and a [[cycle time]] of 1.65 µseconds. It connected to the so-called [[PDP-10 Memory Bus\|external memory bus]] of the 18-bit [[address]] form.

	It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

← Older revision		Revision as of 11:21, 23 April 2022
Line 5:		Line 5:
	Each port could be independently set for its address, and for two-way [[interleaving]] (using [[address]] bits 21 and 35).		Each port could be independently set for its address, and for two-way [[interleaving]] (using [[address]] bits 21 and 35).

−	[[Category: PDP-10 ~~memories~~]]	+	[[Category: PDP-10 Memories]]

← Older revision		Revision as of 12:21, 10 January 2021
Line 1:		Line 1:
−	The '''MB10''' was a [[core memory\|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MB10 contained 16KW; [[parity]] was provided to protect the memory contents-. It had an [[access time]] of 0.60 μseconds, and a [[cycle time]] of 1.65 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.	+	The '''MB10''' was a [[core memory\|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MB10 contained 16KW; [[parity]] was provided to protect the memory contents. It had an [[access time]] of 0.60 μseconds, and a [[cycle time]] of 1.65 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.

	It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

← Older revision		Revision as of 22:10, 18 April 2020
Line 1:		Line 1:
−	The '''MB10''' was a [[core memory\|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MB10 contained 16KW. It had an [[access time]] of 0.60 μseconds, and a [[cycle time]] of 1.65 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.	+	The '''MB10''' was a [[core memory\|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MB10 contained 16KW; [[parity]] was provided to protect the memory contents-. It had an [[access time]] of 0.60 μseconds, and a [[cycle time]] of 1.65 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.

	It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

← Older revision		Revision as of 13:07, 12 March 2019
Line 1:		Line 1:
−	The '''MB10''' was a [[core memory\|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MB10 contained 16KW, and ~~had~~ a [[cycle time]] of 1.65 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.	+	The '''MB10''' was a [[core memory\|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MB10 contained 16KW. It had an [[access time]] of 0.60 μseconds, and a [[cycle time]] of 1.65 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.

	It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

← Older revision		Revision as of 02:33, 7 March 2019
Line 1:		Line 1:
−	The '''MB10''' was a [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MB10 contained 16KW, and had a [[cycle time]] of 1.65 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.	+	The '''MB10''' was a [[core memory\|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MB10 contained 16KW, and had a [[cycle time]] of 1.65 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.

	It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

@@ Line 1: / Line 1: @@
-The '''MB-10''' was a [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MB10 contained 16KW, and had a [[cycle time]] of 1.65 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.
+The '''MB10''' was a [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MB10 contained 16KW, and had a [[cycle time]] of 1.65 µseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.
-It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by  [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
+It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by  [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
 Each port could be independently set for its address, and for two-way [[interleaving]] (using [[address]] bits 21 and 35).
 [[Category: PDP-10 memories]]