MB20 core memory - Revision history

Jnc: interleaving cleanup

2023-08-01T02:17:30Z

interleaving cleanup

Jnc: +link

2022-10-24T13:52:34Z

+link

Jnc: cat caps

2022-04-22T12:47:08Z

cat caps

Jnc: /* External links */ +Manual, FMPS

2021-10-17T10:54:04Z

‎External links: +Manual, FMPS

Jnc: DEC doc conflict

2021-04-11T15:01:04Z

DEC doc conflict

Jnc: details on 4-way interleave

2019-03-24T19:27:15Z

details on 4-way interleave

Jnc: +interleaving details

2019-03-24T00:47:21Z

+interleaving details

Jnc: Basics - still trying to understand interleaving

2019-03-20T19:22:48Z

Basics - still trying to understand interleaving

New page

The '''MB20''' was a [[core memory|core]] [[main memory]] system for the later [[PDP-10]]s, principally the mid-period [[KL10]]. An MB20 contained up to four memory controllers, each with up to four 32KW storage modules, for a maximum of 512KW; [[parity]] is provided to protect the memory contents. The [[access time]] is 1.04 µseconds, and the [[cycle time]] is 1.92 µseconds (both for the first [[word]] in a 4-word block, using four-way [[interleaving]]).

It connected to the so-called internal memory bus, the S-Bus, which performs memory transfers in blocks of 4 words, so that 4 words can be read in any cycle. The KL10 contains a pair of S-Busses; controllers 0 and 1 are connected to S-Bus 0, and controllers 2 and 3 to S-Bus 1.

[[Category: PDP-10 memories]]

← Older revision		Revision as of 02:17, 1 August 2023
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−	The '''MB20''' was a [[core memory\|core]] [[main memory]] system for the later [[PDP-10]]s, principally the mid-period [[KL10]]. An MB20 contained up to four memory controllers<sup>*</sup>, each with up to four 32KW storage modules, for a maximum of 512KW; [[parity]] is provided to protect the memory contents. The [[access time]] is 1.04 µseconds, and the [[cycle time]] is 1.92 µseconds (both for the first [[word]] in a 4-word block, using four-way [[interleaving]]).	+	The '''MB20''' was a [[core memory\|core]] [[main memory]] system for the later [[PDP-10]]s, principally the mid-period [[KL10]]. An MB20 contained up to four memory controllers<sup>*</sup>, each with up to four 32KW storage modules, for a maximum of 512KW; [[parity]] is provided to protect the memory contents. The [[access time]] is 1.04 µseconds, and the [[cycle time]] is 1.92 µseconds (both for the first [[word]] in a 4-word block, using four-way [[memory interleaving\|interleaving]]).

	It connected to the KL10's so-called internal memory bus, the [[PDP-10 Memory Bus\|S-Bus]]; controllers 0 and 1 are connected to S-Bus 0, and controllers 2 and 3 to S-Bus 1. For interleaving, each controller is configured as to which addresses (out of the 4 in an S-Bus block) it will respond to; both 2-way and 4-way interleaving require controllers to be set to 'odd' or 'even'. In 4-way interleaving, in addition to two controllers being actuated at the same time, each controller can start two modules reading at the same time.		It connected to the KL10's so-called internal memory bus, the [[PDP-10 Memory Bus\|S-Bus]]; controllers 0 and 1 are connected to S-Bus 0, and controllers 2 and 3 to S-Bus 1. For interleaving, each controller is configured as to which addresses (out of the 4 in an S-Bus block) it will respond to; both 2-way and 4-way interleaving require controllers to be set to 'odd' or 'even'. In 4-way interleaving, in addition to two controllers being actuated at the same time, each controller can start two modules reading at the same time.

@@ Line 1: / Line 1: @@
 The '''MB20''' was a [[core memory|core]] [[main memory]] system for the later [[PDP-10]]s, principally the mid-period [[KL10]]. An MB20 contained up to four memory controllers<sup>*</sup>, each with up to four 32KW storage modules, for a maximum of 512KW; [[parity]] is provided to protect the memory contents. The [[access time]] is 1.04 µseconds, and the [[cycle time]] is 1.92 µseconds (both for the first [[word]] in a 4-word block, using four-way [[interleaving]]).
-It connected to the KL10's so-called internal memory bus, the S-Bus; controllers 0 and 1 are connected to S-Bus 0, and controllers 2 and 3 to S-Bus 1. For interleaving, each controller is configured as to which addresses (out of the 4 in an S-Bus block) it will respond to; both 2-way and 4-way interleaving require controllers to be set to 'odd' or 'even'. In 4-way interleaving, in addition to two controllers being actuated at the same time, each controller can start two modules reading at the same time.
+It connected to the KL10's so-called internal memory bus, the [[PDP-10 Memory Bus|S-Bus]]; controllers 0 and 1 are connected to S-Bus 0, and controllers 2 and 3 to S-Bus 1. For interleaving, each controller is configured as to which addresses (out of the 4 in an S-Bus block) it will respond to; both 2-way and 4-way interleaving require controllers to be set to 'odd' or 'even'. In 4-way interleaving, in addition to two controllers being actuated at the same time, each controller can start two modules reading at the same time.
 <nowiki>*</nowiki> - <i>DEC documentation conflicts on this; the 'MB20 Internal Memory Unit Description', EK-MB020-UD-001, December 1976, says optionally four (pg. 1-1) - and has generally been followed for this writeup; the 'DECsystem-10 DECSYSTEM-20 Processor Reference Manual', AA-H391A-TK, July 1980, says two (pg. G-18).</i>

← Older revision		Revision as of 12:47, 22 April 2022
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	* [http://www.bitsavers.org/pdf/dec/pdp10/memory/MP00179_MB20_Schematic_Aug76.pdf MB20 Field Maintenance Print Set] (MP00179)		* [http://www.bitsavers.org/pdf/dec/pdp10/memory/MP00179_MB20_Schematic_Aug76.pdf MB20 Field Maintenance Print Set] (MP00179)

−	[[Category: PDP-10 ~~memories~~]]	+	[[Category: PDP-10 Memories]]

← Older revision		Revision as of 10:54, 17 October 2021
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	* [[MA20 core memory]]		* [[MA20 core memory]]
		+
		+	==External links==
		+
		+	* [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-MB020-UD-001_Dec76.pdf MB20 Internal Memory Unit Description] (EK-MB020-UD-001)
		+	* [http://www.bitsavers.org/pdf/dec/pdp10/memory/MP00179_MB20_Schematic_Aug76.pdf MB20 Field Maintenance Print Set] (MP00179)

	[[Category: PDP-10 memories]]		[[Category: PDP-10 memories]]

@@ Line 1: / Line 1: @@
-The '''MB20''' was a [[core memory|core]] [[main memory]] system for the later [[PDP-10]]s, principally the mid-period [[KL10]]. An MB20 contained up to four memory controllers, each with up to four 32KW storage modules, for a maximum of 512KW; [[parity]] is provided to protect the memory contents. The [[access time]] is 1.04 µseconds, and the [[cycle time]] is 1.92 µseconds (both for the first [[word]] in a 4-word block, using four-way [[interleaving]]).
+The '''MB20''' was a [[core memory|core]] [[main memory]] system for the later [[PDP-10]]s, principally the mid-period [[KL10]]. An MB20 contained up to four memory controllers<sup>*</sup>, each with up to four 32KW storage modules, for a maximum of 512KW; [[parity]] is provided to protect the memory contents. The [[access time]] is 1.04 µseconds, and the [[cycle time]] is 1.92 µseconds (both for the first [[word]] in a 4-word block, using four-way [[interleaving]]).
 It connected to the KL10's so-called internal memory bus, the S-Bus; controllers 0 and 1 are connected to S-Bus 0, and controllers 2 and 3 to S-Bus 1. For interleaving, each controller is configured as to which addresses (out of the 4 in an S-Bus block) it will respond to; both 2-way and 4-way interleaving require controllers to be set to 'odd' or 'even'. In 4-way interleaving, in addition to two controllers being actuated at the same time, each controller can start two modules reading at the same time.
 [[Category: PDP-10 memories]]