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The '''MCA25 KL Cache/Paging Upgrade''' was an optional improvement for the [[KL10]] [[PDP-10]] [[Central Processing Unit|CPU]]; it replaced the earlier MCA20 Cache. It increased the size of both the [[main memory]] [[cache]], and the [[virtual memory|paging]] cache; it also improved the functionality of the latter. It required CPU [[backplane]] modifications (whether additional wires, or a new backplane, is not yet clear). A KL10 with an MCA25 installed was denominated as a 'KL10-PW'.

The main memory cache of the MCA25, used to hold [[instruction]]s and [[operand]]s, had 1024 4-word location sets (twice as many as the MCA20), divided into 4 'quarters'. Any location in main memory was associated with one entry in each quarter (i.e. this cache is 'four-way set associative'); when allocating a location set for a new entry, the least recently used of the 4 was chosen.

There were two improvements to the 512-entry paging cache (which cached entries from the [[page table]], kept in main memory):

* it was improved to a two-way associative (so that references to two [[virtual address]]es that mapped to the same paging cache entry did not cause it to be constantly reloaded), i.e. doubling the number of entries overall;
* a 'keep' bit was added to each entry, so that page table entries that would be the same in multiple [[process]]es could be retained in the paging cache when it was flushed when switching processes.

The MCA25 consisted of 9 [[DEC card form factor|hex]] cards, of 6 types:

* M852 Cache Directory
* M853 Cache Extension
* M854 Physical Memory Address
* M855 2-Way Associative Pager
* 4 x M856 Cache Data
* M857 MBox Control

All of these are different from the boards in the MCA20.

==External links==

* [http://www.bitsavers.org/pdf/dec/pdp10/KL10/EK-OKL10-TM_KL10_TechRef_Aug84.pdf KL10-Based Technical Manual] (EK-OKL10-TM-002) - the MCA25 is covered in Appendix A (pp. 148-160 of the PDF)
* [http://www.bitsavers.org/pdf/dec/pdp10/KL10/MP01910_MCA25_Cache_Pager_Engineering_Drawings_Jul84.pdf MCA25 Field Maintenance Print Set] (MP01910-01)

[[Category: PDP-10 Processors]]

← Older revision		Revision as of 16:10, 14 November 2023
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−	The '''MCA25 KL Cache/Paging Upgrade''' was an optional improvement for the [[KL10]] [[PDP-10]] [[Central Processing Unit\|CPU]]; it replaced the earlier MCA20 Cache. It increased the size of both the [[main memory]] [[cache]], and the [[virtual memory\|paging]] cache; it also improved the functionality of the latter. It required CPU [[backplane]] modifications (whether additional wires, or a new backplane, is not yet clear). A KL10 with an MCA25 installed was denominated as a 'KL10-PW'.	+	The '''MCA25 KL Cache/Paging Upgrade''' was an optional improvement for the [[KL10]] [[PDP-10]] [[Central Processing Unit\|CPU]]; it replaced the earlier [[MCA20 Cache]]. It increased the size of both the [[main memory]] [[cache]], and the [[virtual memory\|paging]] cache; it also improved the functionality of the latter. It required CPU [[backplane]] modifications (whether additional wires, or a new backplane, is not yet clear). A KL10 with an MCA25 installed was denominated as a 'KL10-PW'.

	The main memory cache of the MCA25, used to hold [[instruction]]s and [[operand]]s, had 1024 4-word location sets (twice as many as the MCA20), divided into 4 'quarters'. Any location in main memory was associated with one entry in each quarter (i.e. this cache is 'four-way set associative'); when allocating a location set for a new entry, the least recently used of the 4 was chosen.		The main memory cache of the MCA25, used to hold [[instruction]]s and [[operand]]s, had 1024 4-word location sets (twice as many as the MCA20), divided into 4 'quarters'. Any location in main memory was associated with one entry in each quarter (i.e. this cache is 'four-way set associative'); when allocating a location set for a new entry, the least recently used of the 4 was chosen.

MCA25 KL Cache/Paging Upgrade - Revision history

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Jnc: Covers the main points