MD10 core memory - Revision history

Jnc: interleaving cleanup

2023-08-02T11:54:10Z

interleaving cleanup

Jnc: +link

2022-10-24T15:09:22Z

+link

Jnc: cat caps

2022-04-23T11:22:09Z

cat caps

Jnc: big-endian numbering

2021-04-19T19:28:07Z

big-endian numbering

Jnc: +parity, access time

2019-03-10T00:53:45Z

+parity, access time

Jnc: typo

2019-03-07T02:16:57Z

typo

Jnc: Add details

2019-03-06T02:11:00Z

Add details

Jnc: add core link

2019-03-06T00:05:35Z

add core link

Jnc: The basics

2019-03-05T03:49:17Z

The basics

New page

The '''MD-10''' was a [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MD10 could contain up to four 32KW memory modules, for a maximum of 128KW. The cycle time is 1.8 μseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.

It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.

[[Category: PDP-10 memories]]

@@ Line 3: / Line 3: @@
 It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by  [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
-Each port on each module could be independently set for its address, and for two-way [[interleaving]] (using address bits 20 and 35); each port can also be four-way interleaved (on all modules at once), using address bits 19 and 34 (recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit).
+Each port on each module could be independently set for its address, and for two-way [[memory interleaving|interleaving]] (using address bits 20 and 35); each port can also be four-way interleaved (on all modules at once), using address bits 19 and 34 (recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit).
 Internal interleaving (among modules in a single MD10) is not productive; the whole MD10 is tied up whenever any module is active.

← Older revision		Revision as of 15:09, 24 October 2022
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−	The '''MD10''' was a [[core memory\|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MD10 could contain two to four 32KW memory modules, for a maximum of 128KW; [[access time]] is 0.8 μseconds, and the [[cycle time]] is a maximum of 1.8 μseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form; [[parity]] is provided to protect the memory contents.	+	The '''MD10''' was a [[core memory\|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MD10 could contain two to four 32KW memory modules, for a maximum of 128KW; [[access time]] is 0.8 μseconds, and the [[cycle time]] is a maximum of 1.8 μseconds. It connected to the so-called [[PDP-10 Memory Bus\|external memory bus]] of the 18-bit [[address]] form; [[parity]] is provided to protect the memory contents.

	It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

← Older revision		Revision as of 11:22, 23 April 2022
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	* [[PDP-10 memories]]		* [[PDP-10 memories]]

−	[[Category: PDP-10 ~~memories~~]]	+	[[Category: PDP-10 Memories]]

@@ Line 3: / Line 3: @@
 It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by  [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
-Each port on each module could be independently set for its address, and for two-way [[interleaving]] (using address bits 20 and 35); each port can also be four-way interleaved (on all modules at once), using address bits 19 and 34.
+Each port on each module could be independently set for its address, and for two-way [[interleaving]] (using address bits 20 and 35); each port can also be four-way interleaved (on all modules at once), using address bits 19 and 34 (recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit).
 Internal interleaving (among modules in a single MD10) is not productive; the whole MD10 is tied up whenever any module is active.
 Each port and each module can independently be completely disabled (i.e. all modules from a single port, or all ports from a single module; but not a single module from a single port).
 [[Category: PDP-10 memories]]

← Older revision		Revision as of 00:53, 10 March 2019
Line 1:		Line 1:
−	The '''MD10''' was a [[core memory\|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MD10 could contain up to four 32KW memory modules, for a maximum of 128KW; the [[cycle time]] is a maximum of 1.8 μseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.	+	The '''MD10''' was a [[core memory\|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MD10 could contain two to four 32KW memory modules, for a maximum of 128KW; [[access time]] is 0.8 μseconds, and the [[cycle time]] is a maximum of 1.8 μseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form; [[parity]] is provided to protect the memory contents.

	It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

← Older revision		Revision as of 02:16, 7 March 2019
Line 1:		Line 1:
−	The '''~~MD-10~~''' was a [[core memory\|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MD10 could contain up to four 32KW memory modules, for a maximum of 128KW; the [[cycle time]] is a maximum of 1.8 μseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.	+	The '''MD10''' was a [[core memory\|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MD10 could contain up to four 32KW memory modules, for a maximum of 128KW; the [[cycle time]] is a maximum of 1.8 μseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.

	It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

@@ Line 1: / Line 1: @@
-The '''MD-10''' was a [[core memory|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MD10 could contain up to four 32KW memory modules, for a maximum of 128KW. The cycle time is 1.8 μseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.
+The '''MD-10''' was a [[core memory|core]] [[main memory]] system for the early [[PDP-10]]s, principally the [[KA10]]. An MD10 could contain up to four 32KW memory modules, for a maximum of 128KW; the [[cycle time]] is a maximum of 1.8 μseconds. It connected to the so-called external memory bus of the 18-bit [[address]] form.
 It was a [[multi-port memory]], with 4 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by  [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
 [[Category: PDP-10 memories]]