ME10 core memory - Revision history

Jnc: interleaving cleanup

2023-08-02T11:55:31Z

interleaving cleanup

← Older revision		Revision as of 11:55, 2 August 2023
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	It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

	Each port could be independently set for its address, and for either 2- or 4-way [[interleaving]] (using [[address]] bits 21 and 35, and bits 20 and 34, respectively; recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit).		Each port could be independently set for its address, and for either 2- or 4-way [[memory interleaving\|interleaving]] (using [[address]] bits 21 and 35, and bits 20 and 34, respectively; recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit).

	[[Category: PDP-10 Memories]]		[[Category: PDP-10 Memories]]

Jnc: +link

2022-10-24T14:00:39Z

+link

← Older revision		Revision as of 14:00, 24 October 2022
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	The '''ME10''' was a [[core memory\|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]]. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form; address bits 14-17 can be set to 'ignore' when an ME10 is connected to a [[KA10]], which uses the 18-bit bus version. [[Parity]] is provided to protect the memory contents. An ME10 contained 16KW; it had an [[access time]] of .55 µseconds (maximum .61 µseconds) and a [[cycle time]] of 1.0 µseconds.		The '''ME10''' was a [[core memory\|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]]. It connected to the so-called [[PDP-10 Memory Bus\|external memory bus]] of either the 18-bit or 22-bit [[address]] form; address bits 14-17 can be set to 'ignore' when an ME10 is connected to a [[KA10]], which uses the 18-bit bus version. [[Parity]] is provided to protect the memory contents. An ME10 contained 16KW; it had an [[access time]] of .55 µseconds (maximum .61 µseconds) and a [[cycle time]] of 1.0 µseconds.

	It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

Jnc: cat caps

2022-04-23T11:23:44Z

cat caps

← Older revision		Revision as of 11:23, 23 April 2022
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	The '''ME10''' was a [[core memory\|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]]. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form; address bits 14-17 can be set to 'ignore' when an ME10 is connected to a [[KA10]], which uses the 18-bit bus version. [[Parity]] is provided to protect the memory contents. An ME10 contained 16KW; it had an [[access time]] of .55 µseconds (maximum .61 µseconds) and a [[cycle time]] of 1.0 µseconds.		The '''ME10''' was a [[core memory\|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]]. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form; address bits 14-17 can be set to 'ignore' when an ME10 is connected to a [[KA10]], which uses the 18-bit bus version. [[Parity]] is provided to protect the memory contents. An ME10 contained 16KW; it had an [[access time]] of .55 µseconds (maximum .61 µseconds) and a [[cycle time]] of 1.0 µseconds.

	It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

	Each port could be independently set for its address, and for either 2- or 4-way [[interleaving]] (using [[address]] bits 21 and 35, and bits 20 and 34, respectively; recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit).		Each port could be independently set for its address, and for either 2- or 4-way [[interleaving]] (using [[address]] bits 21 and 35, and bits 20 and 34, respectively; recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit).

	[[Category: PDP-10 ~~memories~~]]		[[Category: PDP-10 Memories]]

Jnc: typo

2021-04-19T14:35:15Z

typo

← Older revision		Revision as of 14:35, 19 April 2021
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	It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

	Each port could be independently set for its address, and for either 2- or 4-way [[interleaving]] (using [[address]] bits 21 and 35, and bits 20 and 34, respectively; recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-~~ordeb~~ bit).		Each port could be independently set for its address, and for either 2- or 4-way [[interleaving]] (using [[address]] bits 21 and 35, and bits 20 and 34, respectively; recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit).

	[[Category: PDP-10 memories]]		[[Category: PDP-10 memories]]

Jnc: big-endian numbering, 18/22 config

2021-04-19T14:27:47Z

big-endian numbering, 18/22 config

← Older revision		Revision as of 14:27, 19 April 2021
Line 1:		Line 1:
	The '''ME10''' was a [[core memory\|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]]. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form; [[~~parity~~]] is provided to protect the memory contents. An ME10 contained 16KW; it had an [[access time]] of .55 µseconds (maximum .61 µseconds) and a [[cycle time]] of 1.0 µseconds.		The '''ME10''' was a [[core memory\|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]]. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form; address bits 14-17 can be set to 'ignore' when an ME10 is connected to a [[KA10]], which uses the 18-bit bus version. [[Parity]] is provided to protect the memory contents. An ME10 contained 16KW; it had an [[access time]] of .55 µseconds (maximum .61 µseconds) and a [[cycle time]] of 1.0 µseconds.

	It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

	Each port could be independently set for its address, and for either 2- or 4-way [[interleaving]] (using [[address]] bits 21 and 35, and bits 20 and 34, respectively).		Each port could be independently set for its address, and for either 2- or 4-way [[interleaving]] (using [[address]] bits 21 and 35, and bits 20 and 34, respectively; recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-ordeb bit).

	[[Category: PDP-10 memories]]		[[Category: PDP-10 memories]]

Jnc: max access time

2021-01-10T10:52:29Z

max access time

← Older revision		Revision as of 10:52, 10 January 2021
Line 1:		Line 1:
	The '''ME10''' was a [[core memory\|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]]. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form; [[parity]] is provided to protect the memory contents. An ME10 contained 16KW; it had an [[access time]] pf .55 µseconds and a [[cycle time]] of 1.0 µseconds.		The '''ME10''' was a [[core memory\|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]]. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form; [[parity]] is provided to protect the memory contents. An ME10 contained 16KW; it had an [[access time]] of .55 µseconds (maximum .61 µseconds) and a [[cycle time]] of 1.0 µseconds.

	It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

Jnc: +parity, access time

2019-03-10T00:47:37Z

+parity, access time

← Older revision		Revision as of 00:47, 10 March 2019
Line 1:		Line 1:
	The '''ME10''' was a [[core memory\|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]]. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form. An ME10 contained 16KW, and ~~had~~ a [[cycle time]] of 1.0 µseconds.		The '''ME10''' was a [[core memory\|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]]. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form; [[parity]] is provided to protect the memory contents. An ME10 contained 16KW; it had an [[access time]] pf .55 µseconds and a [[cycle time]] of 1.0 µseconds.

	It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

Jnc: +core

2019-03-07T02:31:10Z

+core

← Older revision		Revision as of 02:31, 7 March 2019
Line 1:		Line 1:
	The '''ME10''' was a [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]]. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form. An ME10 contained 16KW, and had a [[cycle time]] of 1.0 µseconds.		The '''ME10''' was a [[core memory\|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]]. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form. An ME10 contained 16KW, and had a [[cycle time]] of 1.0 µseconds.

	It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

Jnc: Covers the basics

2019-03-07T02:05:28Z

Covers the basics

New page

The '''ME10''' was a [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]]. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form. An ME10 contained 16KW, and had a [[cycle time]] of 1.0 µseconds.

It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.

Each port could be independently set for its address, and for either 2- or 4-way [[interleaving]] (using [[address]] bits 21 and 35, and bits 20 and 34, respectively).

[[Category: PDP-10 memories]]