MF10 core memory - Revision history

Jnc: Later CPU's use multiple ports to increase memory bandwidth

2023-11-05T10:37:25Z

Later CPU's use multiple ports to increase memory bandwidth

Jnc: interleaving cleanup

2023-08-02T11:55:55Z

interleaving cleanup

Jnc: +link

2022-10-24T14:00:01Z

+link

Jnc: cat caps

2022-04-23T11:24:42Z

cat caps

Jnc: /* ‎External links */ +Manual

2021-10-17T16:03:15Z

‎‎External links: +Manual

Jnc: big-endian numbering, 18/22 config

2021-04-19T14:33:39Z

big-endian numbering, 18/22 config

Jnc: H216 shared with MM11-L

2020-10-23T15:54:30Z

H216 shared with MM11-L

Jnc: +parity, access time

2019-03-10T03:54:22Z

+parity, access time

Jnc: typos

2019-03-07T19:57:16Z

typos

Jnc: Covers the basics

2019-03-07T02:30:19Z

Covers the basics

New page

The '''MF10''' was a [[core memory|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]], although it was also used on easly [[[KL10]]s. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form. An MF10 contained either 32KW or 64KW, and had a [[cycle time]] of 1.0 µseconds.

It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.

Each port could be independently set for its address, and for either 2- or 4-way [[interleaving]] (using [[address]] bits 35 and 19 or 20, depending on the size; and bits 34 and either 18 or 19. depending; respectively).

[[Category: PDP-10 memories]]

@@ Line 1: / Line 1: @@
 The '''MF10''' was a [[core memory|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]], although it was also used on early [[KL10]]s. It connected to the so-called [[PDP-10 Memory Bus|external memory bus]] of either the 18-bit or 22-bit [[address]] form;  address bits 14-17 can be set to 'ignore' when an ME10 is connected to a [[KA10]], which uses the 18-bit bus version. An MF10 contained either 32KW or 64KW; [[parity]] was provided to protect the memory contents. It had an [[access time]] of 0.61 μseconds, and a [[cycle time]] of 0.95 µseconds.
-It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by  [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
+It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses at least one port (in a [[multi-processor]] system, at least one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
 Each port could be independently set for its address, and for either 2- or 4-way [[memory interleaving|interleaving]] (using [[address]] bits 35 and 19 or 20, depending on the size; and bits 34 and either 18 or 19, depending; respectively - recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit).

@@ Line 3: / Line 3: @@
 It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by  [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
-Each port could be independently set for its address, and for either 2- or 4-way [[interleaving]] (using [[address]] bits 35 and 19 or 20, depending on the size; and bits 34 and either 18 or 19, depending; respectively - recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit).
+Each port could be independently set for its address, and for either 2- or 4-way [[memory interleaving|interleaving]] (using [[address]] bits 35 and 19 or 20, depending on the size; and bits 34 and either 18 or 19, depending; respectively - recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit).
 The maintenance manual (A-MN-MF10-0-MAN-1) discloses that the MF10 shares components with the [[MM11-L core memory]] of the [[PDP-11]]; the H216 core plane of the MF10 is a 19-bit version of the 16-/18-bit H214/H215 of the MM11-L.

← Older revision		Revision as of 14:00, 24 October 2022
Line 1:		Line 1:
−	The '''MF10''' was a [[core memory\|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]], although it was also used on early [[KL10]]s. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form; address bits 14-17 can be set to 'ignore' when an ME10 is connected to a [[KA10]], which uses the 18-bit bus version. An MF10 contained either 32KW or 64KW; [[parity]] was provided to protect the memory contents. It had an [[access time]] of 0.61 μseconds, and a [[cycle time]] of 0.95 µseconds.	+	The '''MF10''' was a [[core memory\|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]], although it was also used on early [[KL10]]s. It connected to the so-called [[PDP-10 Memory Bus\|external memory bus]] of either the 18-bit or 22-bit [[address]] form; address bits 14-17 can be set to 'ignore' when an ME10 is connected to a [[KA10]], which uses the 18-bit bus version. An MF10 contained either 32KW or 64KW; [[parity]] was provided to protect the memory contents. It had an [[access time]] of 0.61 μseconds, and a [[cycle time]] of 0.95 µseconds.

	It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

← Older revision		Revision as of 11:24, 23 April 2022
Line 11:		Line 11:
	* [http://www.bitsavers.org/pdf/dec/pdp10/memory/A-MN-MF10-0-MAN-1_MF10_Core_Memory_Maintenance_Manual_Dec73.pdf MF10 Core Memory Maintenance Manual]		* [http://www.bitsavers.org/pdf/dec/pdp10/memory/A-MN-MF10-0-MAN-1_MF10_Core_Memory_Maintenance_Manual_Dec73.pdf MF10 Core Memory Maintenance Manual]

−	[[Category: PDP-10 ~~memories~~]]	+	[[Category: PDP-10 Memories]]

← Older revision		Revision as of 16:03, 17 October 2021
Line 6:		Line 6:

	The maintenance manual (A-MN-MF10-0-MAN-1) discloses that the MF10 shares components with the [[MM11-L core memory]] of the [[PDP-11]]; the H216 core plane of the MF10 is a 19-bit version of the 16-/18-bit H214/H215 of the MM11-L.		The maintenance manual (A-MN-MF10-0-MAN-1) discloses that the MF10 shares components with the [[MM11-L core memory]] of the [[PDP-11]]; the H216 core plane of the MF10 is a 19-bit version of the 16-/18-bit H214/H215 of the MM11-L.
		+
		+	==External links==
		+
		+	* [http://www.bitsavers.org/pdf/dec/pdp10/memory/A-MN-MF10-0-MAN-1_MF10_Core_Memory_Maintenance_Manual_Dec73.pdf MF10 Core Memory Maintenance Manual]

	[[Category: PDP-10 memories]]		[[Category: PDP-10 memories]]

← Older revision		Revision as of 15:54, 23 October 2020
Line 4:		Line 4:

	Each port could be independently set for its address, and for either 2- or 4-way [[interleaving]] (using [[address]] bits 35 and 19 or 20, depending on the size; and bits 34 and either 18 or 19, depending; respectively).		Each port could be independently set for its address, and for either 2- or 4-way [[interleaving]] (using [[address]] bits 35 and 19 or 20, depending on the size; and bits 34 and either 18 or 19, depending; respectively).
		+
		+	The maintenance manual (A-MN-MF10-0-MAN-1) discloses that the MF10 shares components with the [[MM11-L core memory]] of the [[PDP-11]]; the H216 core plane of the MF10 is a 19-bit version of the 16-/18-bit H214/H215 of the MM11-L.

	[[Category: PDP-10 memories]]		[[Category: PDP-10 memories]]

← Older revision		Revision as of 03:54, 10 March 2019
Line 1:		Line 1:
−	The '''MF10''' was a [[core memory\|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]], although it was also used on early [[KL10]]s. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form. An MF10 contained either 32KW or 64KW, and ~~had~~ a [[cycle time]] of 1.0 µseconds.	+	The '''MF10''' was a [[core memory\|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]], although it was also used on early [[KL10]]s. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form. An MF10 contained either 32KW or 64KW; [[parity]] was provided to protect the memory contents. It had an [[access time]] of 0.61 μseconds, and a [[cycle time]] of 0.95 µseconds.

	It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

@@ Line 1: / Line 1: @@
-The '''MF10''' was a [[core memory|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]], although it was also used on easly [[[KL10]]s. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form. An MF10 contained either 32KW or 64KW, and had a [[cycle time]] of 1.0 µseconds.
+The '''MF10''' was a [[core memory|core]] [[main memory]] system for the mid-period [[PDP-10]]s, principally the [[KI10]], although it was also used on early [[KL10]]s. It connected to the so-called external memory bus of either the 18-bit or 22-bit [[address]] form. An MF10 contained either 32KW or 64KW, and had a [[cycle time]] of 1.0 µseconds.
 It was a [[multi-port memory]], with 4 ports per memory system: each port can be independently disabled. The [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by  [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
-Each port could be independently set for its address, and for either 2- or 4-way [[interleaving]] (using [[address]] bits 35 and 19 or 20, depending on the size; and bits 34 and either 18 or 19. depending; respectively).
+Each port could be independently set for its address, and for either 2- or 4-way [[interleaving]] (using [[address]] bits 35 and 19 or 20, depending on the size; and bits 34 and either 18 or 19, depending; respectively).
 [[Category: PDP-10 memories]]