MF20 MOS memory - Revision history

Jnc: +link

2022-10-24T13:50:52Z

+link

← Older revision		Revision as of 13:50, 24 October 2022
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	The '''MF20''' was a [[Metal Oxide Semiconductor\|MOS]] [[Dynamic RAM\|DRAM]] [[main memory]] system for the later [[PDP-10]]s, principally the final [[KL10]]s (models KL10-E and KL10-R). An MF20 contained up to three storage groups, each with 256KW, for a maximum of 768KW; up to 4 MF20's could be connected to a single system, for a total of up to 3072KW.		The '''MF20''' was a [[Metal Oxide Semiconductor\|MOS]] [[Dynamic RAM\|DRAM]] [[main memory]] system for the later [[PDP-10]]s, principally the final [[KL10]]s (models KL10-E and KL10-R). An MF20 contained up to three storage groups, each with 256KW, for a maximum of 768KW; up to 4 MF20's could be connected to a single system, for a total of up to 3072KW.

	The [[access time]] is .80 µseconds at the [[Central Processing Unit\|CPU]], and the [[cycle time]] is 1.00 µseconds (both for the first [[word]] in a 4-word block). <!-- Refresh time is 570 nsec (typical; 610 nsec maximum); the time for a complete refresh pass is 14.5 μsec (typical), 13.5 μsec (minimum). --> The MF20 connected to the KL10's upgraded internal memory bus, the X-Bus. [[Error-correcting code\|ECC]] is provided to protect the memory contents; an MF20 44-[[bit]] word contains 36 data bits, 6 ECC bits, 1 bit of ECC [[parity]], and 1 spare bit. The MF20 can be configured to switch the spare bit in to temporarily replace a failing bit, until the latter can be replaced		The [[access time]] is .80 µseconds at the [[Central Processing Unit\|CPU]], and the [[cycle time]] is 1.00 µseconds (both for the first [[word]] in a 4-word block). <!-- Refresh time is 570 nsec (typical; 610 nsec maximum); the time for a complete refresh pass is 14.5 μsec (typical), 13.5 μsec (minimum). --> The MF20 connected to the KL10's upgraded internal memory bus, the [[PDP-10 Memory Bus\|X-Bus]]. [[Error-correcting code\|ECC]] is provided to protect the memory contents; an MF20 44-[[bit]] word contains 36 data bits, 6 ECC bits, 1 bit of ECC [[parity]], and 1 spare bit. The MF20 can be configured to switch the spare bit in to temporarily replace a failing bit, until the latter can be replaced

	The sizes above are with 16Kx1 [[integrated circuit\|chips]]; the manual says that 64Kx1 chips would be supported, giving 1024KW for a group, but it's not clear if this was ever produced; although perhaps this was later named the [[MG20 MOS memory]].		The sizes above are with 16Kx1 [[integrated circuit\|chips]]; the manual says that 64Kx1 chips would be supported, giving 1024KW for a group, but it's not clear if this was ever produced; although perhaps this was later named the [[MG20 MOS memory]].

Jnc: /* External links */ +MF20 engineering drawings

2022-06-06T15:03:10Z

External links: +MF20 engineering drawings

← Older revision		Revision as of 15:03, 6 June 2022
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	* [http://www.bitsavers.org/pdf/dec/pdp10/KL10/MF20_TechMan.pdf MOS Memory Subsystem Technical Manual] (EK-0MF20-TM)		* [http://www.bitsavers.org/pdf/dec/pdp10/KL10/MF20_TechMan.pdf MOS Memory Subsystem Technical Manual] (EK-0MF20-TM)
			* [http://bitsavers.org/pdf/dec/pdp10/KL10/MF20_schem_May78.pdf MOS Memory MF20 engineering drawings]
	* [http://www.bitsavers.org/pdf/dec/pdp10/KL10/MP00622_MF20_Oct82.pdf MF20 Field Maintenance Print Set] (MP00622)		* [http://www.bitsavers.org/pdf/dec/pdp10/KL10/MP00622_MF20_Oct82.pdf MF20 Field Maintenance Print Set] (MP00622)

	[[Category: PDP-10 Memories]]		[[Category: PDP-10 Memories]]

Jnc: cat caps

2022-04-22T12:47:44Z

cat caps

← Older revision		Revision as of 12:47, 22 April 2022
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	* [http://www.bitsavers.org/pdf/dec/pdp10/KL10/MP00622_MF20_Oct82.pdf MF20 Field Maintenance Print Set] (MP00622)		* [http://www.bitsavers.org/pdf/dec/pdp10/KL10/MP00622_MF20_Oct82.pdf MF20 Field Maintenance Print Set] (MP00622)

	[[Category: PDP-10 ~~memories~~]]		[[Category: PDP-10 Memories]]

Jnc: Word contents, +External links

2021-10-17T11:50:11Z

Word contents, +External links

← Older revision		Revision as of 11:50, 17 October 2021
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	The '''MF20''' was a [[Metal Oxide Semiconductor\|MOS]] [[Dynamic RAM\|DRAM]] [[main memory]] system for the later [[PDP-10]]s, principally the final [[KL10]]s (models KL10-E and KL10-R). An MF20 contained up to three storage groups, each with 256KW, for a maximum of 768KW; up to 4 MF20's could be connected to a single system, for a total of up to 3072KW.		The '''MF20''' was a [[Metal Oxide Semiconductor\|MOS]] [[Dynamic RAM\|DRAM]] [[main memory]] system for the later [[PDP-10]]s, principally the final [[KL10]]s (models KL10-E and KL10-R). An MF20 contained up to three storage groups, each with 256KW, for a maximum of 768KW; up to 4 MF20's could be connected to a single system, for a total of up to 3072KW.

	The [[access time]] is .80 µseconds at the [[Central Processing Unit\|CPU]], and the [[cycle time]] is 1.00 µseconds (both for the first [[word]] in a 4-word block). <!-- Refresh time is 570 nsec (typical; 610 nsec maximum); the time for a complete refresh pass is 14.5 μsec (typical), 13.5 μsec (minimum). --> [[Error-correcting code\|ECC]] is provided to protect the memory contents. The MF20 ~~connected~~ to the ~~KL10's ugraded internal memory bus~~, the ~~X-Bus.~~		The [[access time]] is .80 µseconds at the [[Central Processing Unit\|CPU]], and the [[cycle time]] is 1.00 µseconds (both for the first [[word]] in a 4-word block). <!-- Refresh time is 570 nsec (typical; 610 nsec maximum); the time for a complete refresh pass is 14.5 μsec (typical), 13.5 μsec (minimum). --> The MF20 connected to the KL10's upgraded internal memory bus, the X-Bus. [[Error-correcting code\|ECC]] is provided to protect the memory contents; an MF20 44-[[bit]] word contains 36 data bits, 6 ECC bits, 1 bit of ECC [[parity]], and 1 spare bit. The MF20 can be configured to switch the spare bit in to temporarily replace a failing bit, until the latter can be replaced

	The sizes above are with 16Kx1 [[integrated circuit\|chips]]; the manual says that 64Kx1 chips would be supported, giving 1024KW for a group, but it's not clear if this was ever produced; although perhaps this was later named the [[MG20 MOS memory]].		The sizes above are with 16Kx1 [[integrated circuit\|chips]]; the manual says that 64Kx1 chips would be supported, giving 1024KW for a group, but it's not clear if this was ever produced; although perhaps this was later named the [[MG20 MOS memory]].

			==External links==

			* [http://www.bitsavers.org/pdf/dec/pdp10/KL10/MF20_TechMan.pdf MOS Memory Subsystem Technical Manual] (EK-0MF20-TM)
			* [http://www.bitsavers.org/pdf/dec/pdp10/KL10/MP00622_MF20_Oct82.pdf MF20 Field Maintenance Print Set] (MP00622)

	[[Category: PDP-10 memories]]		[[Category: PDP-10 memories]]

Jnc: ref MG20

2021-04-10T15:48:32Z

ref MG20

← Older revision		Revision as of 15:48, 10 April 2021
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	The [[access time]] is .80 µseconds at the [[Central Processing Unit\|CPU]], and the [[cycle time]] is 1.00 µseconds (both for the first [[word]] in a 4-word block). <!-- Refresh time is 570 nsec (typical; 610 nsec maximum); the time for a complete refresh pass is 14.5 μsec (typical), 13.5 μsec (minimum). --> [[Error-correcting code\|ECC]] is provided to protect the memory contents. The MF20 connected to the KL10's ugraded internal memory bus, the X-Bus.		The [[access time]] is .80 µseconds at the [[Central Processing Unit\|CPU]], and the [[cycle time]] is 1.00 µseconds (both for the first [[word]] in a 4-word block). <!-- Refresh time is 570 nsec (typical; 610 nsec maximum); the time for a complete refresh pass is 14.5 μsec (typical), 13.5 μsec (minimum). --> [[Error-correcting code\|ECC]] is provided to protect the memory contents. The MF20 connected to the KL10's ugraded internal memory bus, the X-Bus.

	The sizes above are with 16Kx1 [[integrated circuit\|chips]]; the manual says that 64Kx1 chips would be supported, giving 1024KW for a group, but it's not clear if this was ever produced.		The sizes above are with 16Kx1 [[integrated circuit\|chips]]; the manual says that 64Kx1 chips would be supported, giving 1024KW for a group, but it's not clear if this was ever produced; although perhaps this was later named the [[MG20 MOS memory]].

	[[Category: PDP-10 memories]]		[[Category: PDP-10 memories]]

Jnc: typo, order

2019-03-26T00:40:37Z

typo, order

← Older revision		Revision as of 00:40, 26 March 2019
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	The '''MF20''' was a [[Metal Oxide Semiconductor\|MOS]] [[Dynamic RAM\|DRAM]] [[main memory]] system for the later [[PDP-10]]s, principally the final [[KL10]]s (models KL10-E and KL10-R). An MF20 contained up to three storage groups, each with 256KW, for a maximum of 768KW; up to 4 MF20's could be connected to a single system, for a total of up to 3072KW.		The '''MF20''' was a [[Metal Oxide Semiconductor\|MOS]] [[Dynamic RAM\|DRAM]] [[main memory]] system for the later [[PDP-10]]s, principally the final [[KL10]]s (models KL10-E and KL10-R). An MF20 contained up to three storage groups, each with 256KW, for a maximum of 768KW; up to 4 MF20's could be connected to a single system, for a total of up to 3072KW.

	~~[[Error-correcting code\|ECC]] is provided to protect the memory contents.~~ The [[access time]] is .80 µseconds at the [[Central Processing Unit\|CPU]], and the [[cycle time]] is 1.00 µseconds (both for the first [[word]] in a 4-word block). <!-- Refresh time is 570 nsec (typical; 610 nsec maximum); the time for a complete refresh pass is 14.5 μsec (typical), 13.5 μsec (minimum). --> It connected to the KL10's ugraded internal memory bus, the X-Bus.		The [[access time]] is .80 µseconds at the [[Central Processing Unit\|CPU]], and the [[cycle time]] is 1.00 µseconds (both for the first [[word]] in a 4-word block). <!-- Refresh time is 570 nsec (typical; 610 nsec maximum); the time for a complete refresh pass is 14.5 μsec (typical), 13.5 μsec (minimum). --> [[Error-correcting code\|ECC]] is provided to protect the memory contents. The MF20 connected to the KL10's ugraded internal memory bus, the X-Bus.

	The sizes above are with 16Kx1 [[integrated circuit\|chips]]; the manual says that ~~646Kx1~~ chips would be supported, giving 1024KW for a group, but it's not clear if this was ever produced.		The sizes above are with 16Kx1 [[integrated circuit\|chips]]; the manual says that 64Kx1 chips would be supported, giving 1024KW for a group, but it's not clear if this was ever produced.

	[[Category: PDP-10 memories]]		[[Category: PDP-10 memories]]

Jnc: basics, more coming

2019-03-25T01:03:45Z

basics, more coming

New page

The '''MF20''' was a [[Metal Oxide Semiconductor|MOS]] [[Dynamic RAM|DRAM]] [[main memory]] system for the later [[PDP-10]]s, principally the final [[KL10]]s (models KL10-E and KL10-R). An MF20 contained up to three storage groups, each with 256KW, for a maximum of 768KW; up to 4 MF20's could be connected to a single system, for a total of up to 3072KW.

[[Error-correcting code|ECC]] is provided to protect the memory contents. The [[access time]] is .80 µseconds at the [[Central Processing Unit|CPU]], and the [[cycle time]] is 1.00 µseconds (both for the first [[word]] in a 4-word block).  It connected to the KL10's ugraded internal memory bus, the X-Bus.

The sizes above are with 16Kx1 [[integrated circuit|chips]]; the manual says that 646Kx1 chips would be supported, giving 1024KW for a group, but it's not clear if this was ever produced.

[[Category: PDP-10 memories]]