MG10 core memory - Revision history

Jnc: Later C

2023-11-05T10:33:43Z

Later C

Jnc: interleaving cleanup

2023-08-02T11:56:27Z

interleaving cleanup

Jnc: +link

2022-10-24T13:57:38Z

+link

Jnc: cat caps

2022-04-23T11:26:14Z

cat caps

Jnc: boards shared with MM11-U

2021-10-22T02:54:57Z

boards shared with MM11-U

Jnc: /External links: +Manual, FMPS

2021-10-17T19:46:50Z

/External links: +Manual, FMPS

Jnc: big-endian numbering, 18/22 config

2021-04-20T16:12:08Z

big-endian numbering, 18/22 config

Jnc: +parity

2019-03-09T19:52:17Z

+parity

Jnc: More details

2019-03-09T19:25:36Z

More details

Jnc: Covers the basics

2019-03-08T03:27:07Z

Covers the basics

New page

The '''MG10''' was a [[core memory|core]] [[main memory]] system for the [[PDP-10]]s, principally the early [[KL10]]. An MG10 could contain up to four 32KW memory banks, for a maximum of 128KW; the [[access time]] is .67 μseconds maximum, and the [[cycle time]] is 1.0 μseconds. An MG10 contains a pair of 'controllers', with the controller used for any particular cycle selected by [[address]] bit 21.

It was a [[multi-port memory]], with 8 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.

It connected to the so-called external memory bus of the 18-or 22-bit address form. Each port on each module could be independently set to use 18- or 22-bit addresses, or to be disabled. The MG10 supports two-way [[interleaving]] internally to an MG10, and four-way interleaving between a pair of MG10's (provided they are equally sized).

The base address of an MG10 is switch-selectable; that address is used on all the ports, unlike the earlier [[PDP-10 memories]].

[[Category: PDP-10 memories]]

@@ Line 1: / Line 1: @@
 The '''MG10''' was a [[core memory|core]] [[main memory]] system for the [[PDP-10]]s, principally the [[KI10]] and early [[KL10]]s. An MG10 could contain up to four 32KW memory banks, for a maximum of 128KW (only 1, 2 or 4 bank operation is supported, however). The [[access time]] is .67 μseconds maximum, and the [[cycle time]] is 1.0 μseconds; [[parity]] is provided to protect the memory contents. An MG10 contains a pair of 'controllers', with the controller used for any particular cycle selected by [[address]] bit 21.
-It was a [[multi-port memory]], with 8 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by  [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
+It was a [[multi-port memory]], with 8 ports per memory system: the [[Central Processing Unit|CPU]] uses at least one port (in a [[multi-processor]] system, at least one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
 It connected to the so-called [[PDP-10 Memory Bus|external memory bus]] of the KA (18-bit address) or KI (22-bit address) form. Each port could be independently set to use 18- or 22-bit addresses, or to be disabled. The base address of an MG10 is switch-selectable; that address is used on all the ports, unlike the earlier [[PDP-10 memories]].

@@ Line 5: / Line 5: @@
 It connected to the so-called [[PDP-10 Memory Bus|external memory bus]] of the KA (18-bit address) or KI (22-bit address) form. Each port could be independently set to use 18- or 22-bit addresses, or to be disabled. The base address of an MG10 is switch-selectable; that address is used on all the ports, unlike the earlier [[PDP-10 memories]].
-The MG10 supports two-way [[interleaving]] internally to an MG10, and four-way interleaving between a pair of MG10's (provided they are equally sized); any interleaving applies to all ports. For the two-way case, address bits 21 and 35 are exchanged (recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit), so that all even addresses are handled by controller 0, and odd through controller 1.
+The MG10 supports two-way [[memory interleaving|interleaving]] internally to an MG10, and four-way interleaving between a pair of MG10's (provided they are equally sized); any interleaving applies to all ports. For the two-way case, address bits 21 and 35 are exchanged (recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit), so that all even addresses are handled by controller 0, and odd through controller 1.
 The MG10 shares components with the [[MM11-U core memory]] of the [[PDP-11]]: the G114 sense/inhibit and G235 XY Drive cards; and the H217-B core plane of the MG10 is a 19-bit version of the 18-/16-bit H217-C/D of the MM11-U.

@@ Line 3: / Line 3: @@
 It was a [[multi-port memory]], with 8 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by  [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
-It connected to the so-called external memory bus of the KA (18-bit address) or KI (22-bit address) form. Each port could be independently set to use 18- or 22-bit addresses, or to be disabled. The base address of an MG10 is switch-selectable; that address is used on all the ports, unlike the earlier [[PDP-10 memories]].
+It connected to the so-called [[PDP-10 Memory Bus|external memory bus]] of the KA (18-bit address) or KI (22-bit address) form. Each port could be independently set to use 18- or 22-bit addresses, or to be disabled. The base address of an MG10 is switch-selectable; that address is used on all the ports, unlike the earlier [[PDP-10 memories]].
 The MG10 supports two-way [[interleaving]] internally to an MG10, and four-way interleaving between a pair of MG10's (provided they are equally sized); any interleaving applies to all ports. For the two-way case, address bits 21 and 35 are exchanged (recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit), so that all even addresses are handled by controller 0, and odd through controller 1.

← Older revision		Revision as of 11:26, 23 April 2022
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	* [http://www.bitsavers.org/pdf/dec/pdp10/memory/MG10_Schematic_Jun75.pdf MG10 Engineering Drawings]		* [http://www.bitsavers.org/pdf/dec/pdp10/memory/MG10_Schematic_Jun75.pdf MG10 Engineering Drawings]

−	[[Category: PDP-10 ~~memories~~]]	+	[[Category: PDP-10 Memories]]

← Older revision		Revision as of 02:54, 22 October 2021
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	The MG10 supports two-way [[interleaving]] internally to an MG10, and four-way interleaving between a pair of MG10's (provided they are equally sized); any interleaving applies to all ports. For the two-way case, address bits 21 and 35 are exchanged (recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit), so that all even addresses are handled by controller 0, and odd through controller 1.		The MG10 supports two-way [[interleaving]] internally to an MG10, and four-way interleaving between a pair of MG10's (provided they are equally sized); any interleaving applies to all ports. For the two-way case, address bits 21 and 35 are exchanged (recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit), so that all even addresses are handled by controller 0, and odd through controller 1.
		+
		+	The MG10 shares components with the [[MM11-U core memory]] of the [[PDP-11]]: the G114 sense/inhibit and G235 XY Drive cards; and the H217-B core plane of the MG10 is a 19-bit version of the 18-/16-bit H217-C/D of the MM11-U.

	==External links==		==External links==

← Older revision		Revision as of 19:46, 17 October 2021
Line 6:		Line 6:

	The MG10 supports two-way [[interleaving]] internally to an MG10, and four-way interleaving between a pair of MG10's (provided they are equally sized); any interleaving applies to all ports. For the two-way case, address bits 21 and 35 are exchanged (recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit), so that all even addresses are handled by controller 0, and odd through controller 1.		The MG10 supports two-way [[interleaving]] internally to an MG10, and four-way interleaving between a pair of MG10's (provided they are equally sized); any interleaving applies to all ports. For the two-way case, address bits 21 and 35 are exchanged (recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit), so that all even addresses are handled by controller 0, and odd through controller 1.
		+
		+	==External links==
		+
		+	* [http://www.bitsavers.org/pdf/dec/pdp10/memory/EK-MG10-MM-001_MG10_Maintenance_Manual.pdf MG10 Maintenance Manual] (EK-MG10-MM-001)
		+	* [http://www.bitsavers.org/pdf/dec/pdp10/memory/MG10_Schematic_Jun75.pdf MG10 Engineering Drawings]

	[[Category: PDP-10 memories]]		[[Category: PDP-10 memories]]

← Older revision		Revision as of 19:52, 9 March 2019
Line 1:		Line 1:
−	The '''MG10''' was a [[core memory\|core]] [[main memory]] system for the [[PDP-10]]s, principally the early [[KL10]]. An MG10 could contain up to four 32KW memory banks, for a maximum of 128KW (only 1, 2 or 4 bank operation is supported, however). The [[access time]] is .67 μseconds maximum, and the [[cycle time]] is 1.0 μseconds. An MG10 contains a pair of 'controllers', with the controller used for any particular cycle selected by [[address]] bit 21.	+	The '''MG10''' was a [[core memory\|core]] [[main memory]] system for the [[PDP-10]]s, principally the early [[KL10]]. An MG10 could contain up to four 32KW memory banks, for a maximum of 128KW (only 1, 2 or 4 bank operation is supported, however). The [[access time]] is .67 μseconds maximum, and the [[cycle time]] is 1.0 μseconds; [[parity]] is provided to protect the memory contents. An MG10 contains a pair of 'controllers', with the controller used for any particular cycle selected by [[address]] bit 21.

	It was a [[multi-port memory]], with 8 ports per memory system: the [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.		It was a [[multi-port memory]], with 8 ports per memory system: the [[Central Processing Unit\|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel\|DF10]]) for [[mass storage]] such as [[disk]]s.

@@ Line 1: / Line 1: @@
-The '''MG10''' was a [[core memory|core]] [[main memory]] system for the [[PDP-10]]s, principally the early [[KL10]]. An MG10 could contain up to four 32KW memory banks, for a maximum of 128KW; the [[access time]] is .67 μseconds maximum, and the [[cycle time]] is 1.0 μseconds. An MG10 contains a pair of 'controllers', with the controller used for any particular cycle selected by [[address]] bit 21.
+The '''MG10''' was a [[core memory|core]] [[main memory]] system for the [[PDP-10]]s, principally the early [[KL10]]. An MG10 could contain up to four 32KW memory banks, for a maximum of 128KW (only 1, 2 or 4 bank operation is supported, however). The [[access time]] is .67 μseconds maximum, and the [[cycle time]] is 1.0 μseconds. An MG10 contains a pair of 'controllers', with the controller used for any particular cycle selected by [[address]] bit 21.
 It was a [[multi-port memory]], with 8 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by  [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
-It connected to the so-called external memory bus of the 18-or 22-bit address form. Each port on each module could be independently set to use 18- or 22-bit addresses, or to be disabled. The MG10 supports two-way [[interleaving]] internally to an MG10, and four-way interleaving between a pair of MG10's (provided they are equally sized).
+It connected to the so-called external memory bus of the 18-or 22-bit address form. Each port on each module could be independently set to use 18- or 22-bit addresses, or to be disabled. The base address of an MG10 is switch-selectable; that address is used on all the ports, unlike the earlier [[PDP-10 memories]].
-The base address of an MG10 is switch-selectable; that address is used on all the ports, unlike the earlier [[PDP-10 memories]].
+The MG10 supports two-way [[interleaving]] internally to an MG10, and four-way interleaving between a pair of MG10's (provided they are equally sized); any interleaving applies to all ports. For the two-way case, address bits 21 and 35 are exchanged, so that all even addresses are handled by controller 0, and odd through controller 1.
 [[Category: PDP-10 memories]]