MG20 MOS memory - Revision history

Jnc: +link

2022-10-24T13:49:40Z

+link

Jnc: typo

2022-04-22T12:49:27Z

typo

Jnc: cat caps

2022-04-22T12:48:33Z

cat caps

Jnc: Word contents, +External links

2021-10-17T13:23:29Z

Word contents, +External links

Jnc: /* See also */ +1

2021-04-10T15:45:52Z

‎See also: +1

Jnc: any kind

2019-04-06T20:10:09Z

any kind

Jnc: An OK overview

2019-03-28T01:06:42Z

An OK overview

New page

The '''MG20''' was a [[Metal Oxide Semiconductor|MOS]] [[Dynamic RAM|DRAM]] [[main memory]] system for the later [[PDP-10]]s, principally the final [[KL10]]s (models KL10-E and KL10-R). An MG20 contained up to two storage groups, each with 1MW, for a maximum of 2MW; up to 2 MG20's could be connected to a single system, for a total of up to 4M.

The MG20 was basically an [[MF20 MOS memory|MF20]] with 64Kx1 [[integrated circuit|chips]], instead of the 16Kx1 chips of the MF20. It appears that it was possible to upgrade an MF20 to an MG20 by replacing the four M8579 MOS Memory cards of each storage group of the MF20 with the M8570 MOS Memory cards of the MG20, and upgrading the [[power supply]]; the four control cards of the MF20:

* M8574 Write Path
* M8575 Syndrome
* M8576 Control and Timing
* M8577 Address and Timing

remained unchanged.


[[Error-correcting code|ECC]] is provided to protect the memory contents. The MG20 connected to the KL10's ugraded internal memory bus, the X-Bus. The MG20 was [[multi-port memory|single-port memory]], and could not be used in [[multi-processor|symmetric multi-processor]] systems, or with external [[channel]]s.

[[Category: PDP-10 memories]]

@@ Line 13: / Line 13: @@
 [[Error-correcting code|ECC]] is provided to protect the memory contents; the MG20 almost certainly shared the MF20's 44-[[bit]] word, which contained 36 data bits, 6 ECC bits, 1 bit of ECC [[parity]], and 1 spare bit. The MG20 could almost certainly be similarly configured to switch the spare bit in to temporarily replace a failing bit, until the latter could be replaced.
-The MG20 also connected to the KL10's upgraded internal memory bus, the X-Bus. The MG20 was [[multi-port memory|single-port memory]], and could not be used in a [[multi-processor]] system, or with external [[channel]]s.
+The MG20 also connected to the KL10's upgraded internal memory bus, the [[PDP-10 Memory Bus|X-Bus]]. The MG20 was [[multi-port memory|single-port memory]], and could not be used in a [[multi-processor]] system, or with external [[channel]]s.
 ==See also==

@@ Line 13: / Line 13: @@
 [[Error-correcting code|ECC]] is provided to protect the memory contents; the MG20 almost certainly shared the MF20's 44-[[bit]] word, which contained 36 data bits, 6 ECC bits, 1 bit of ECC [[parity]], and 1 spare bit. The MG20 could almost certainly be similarly configured to switch the spare bit in to temporarily replace a failing bit, until the latter could be replaced.
-The MG20 also connected to the KL10's ugraded internal memory bus, the X-Bus. The MG20 was [[multi-port memory|single-port memory]], and could not be used in a [[multi-processor]] system, or with external [[channel]]s.
+The MG20 also connected to the KL10's upgraded internal memory bus, the X-Bus. The MG20 was [[multi-port memory|single-port memory]], and could not be used in a [[multi-processor]] system, or with external [[channel]]s.
 ==See also==

← Older revision		Revision as of 12:48, 22 April 2022
Line 24:		Line 24:
	* [http://www.bitsavers.org/pdf/dec/pdp10/KL10/MP01904_MG20_Jun84.pdf MG20 Field Maintenance Print Set] (MP01904)		* [http://www.bitsavers.org/pdf/dec/pdp10/KL10/MP01904_MG20_Jun84.pdf MG20 Field Maintenance Print Set] (MP01904)

−	[[Category: PDP-10 ~~memories~~]]	+	[[Category: PDP-10 Memories]]

@@ Line 1: / Line 1: @@
-The '''MG20''' was a [[Metal Oxide Semiconductor|MOS]] [[Dynamic RAM|DRAM]] [[main memory]] system for the later [[PDP-10]]s, principally the final [[KL10]]s (models KL10-E and KL10-R). An MG20 contained up to two storage groups, each with 1MW, for a maximum of 2MW; up to 2 MG20's could be connected to a single system, for a total of up to 4M.
+The '''MG20''' was a [[Metal Oxide Semiconductor|MOS]] [[Dynamic RAM|DRAM]] [[main memory]] system for the later [[PDP-10]]s, principally the final [[KL10]]s (models KL10-E and KL10-R). An MG20 contained up to three storage groups, each with 1MW, for a maximum of 3MW; up to 2 MG20's could be connected to a single system, for a total of up to 4M (the limit is in software).
 The MG20 was basically an [[MF20 MOS memory|MF20]] with 64Kx1 [[integrated circuit|chips]], instead of the 16Kx1 chips of the MF20. It appears that it was possible to upgrade an MF20 to an MG20 by replacing the four M8579 MOS Memory cards of each storage group of the MF20 with the M8570 MOS Memory cards of the MG20, and upgrading the [[power supply]]; the four control cards of the MF20:
@@ Line 11: / Line 11: @@
 <!-- The [[access time]] is .80 µseconds at the [[Central Processing Unit|CPU]], and the [[cycle time]] is 1.00 µseconds (both for the first [[word]] in a 4-word block). Refresh time is 570 nsec (typical; 610 nsec maximum); the time for a complete refresh pass is 14.5 μsec (typical), 13.5 μsec (minimum). -->
-[[Error-correcting code|ECC]] is provided to protect the memory contents. The MG20 connected to the KL10's ugraded internal memory bus, the X-Bus. The MG20 was [[multi-port memory|single-port memory]], and could not be used in a [[multi-processor]] system, or with external [[channel]]s.
+[[Error-correcting code|ECC]] is provided to protect the memory contents; the MG20 almost certainly shared the MF20's 44-[[bit]] word, which contained 36 data bits, 6 ECC bits, 1 bit of ECC [[parity]], and 1 spare bit. The MG20 could almost certainly be similarly configured to switch the spare bit in to temporarily replace a failing bit, until the latter could be replaced.
 ==See also==
 * [[MF20 MOS memory]]
 [[Category: PDP-10 memories]]