MH10 core memory - Revision history

Jnc: Later CPU's use multiple ports to increase memory bandwidth

2023-11-05T10:40:08Z

Later CPU's use multiple ports to increase memory bandwidth

Jnc: interleaving cleanup

2023-08-02T11:57:12Z

interleaving cleanup

Jnc: +link

2022-10-24T13:56:55Z

+link

Jnc: cat caps

2022-04-23T11:27:25Z

cat caps

Jnc: boards shared with MM11-W

2021-10-22T03:39:59Z

boards shared with MM11-W

Jnc: /* External links */ +Manual, FMPS

2021-10-17T19:53:44Z

‎External links: +Manual, FMPS

Jnc: big-endian numbering, 18/22 config, bank enable/dis

2021-04-20T16:17:09Z

big-endian numbering, 18/22 config, bank enable/dis

Jnc: typo; note doc clash

2021-04-13T17:55:30Z

typo; note doc clash

Jnc: Covers the basics

2019-03-09T19:51:37Z

Covers the basics

New page

The '''MH10''' was a [[core memory|core]] [[main memory]] system for the [[PDP-10]]s, principally the early [[KL10]]. An MG10 could contain up to four 64KW memory banks, for a maximum of 256KW (only 1, 2 or 4 bank operation is supported, however). The [[access time]] is .74 µseconds, and the [[cycle time]] is 1.18 µseconds; [[parity]] is provided to protect the memory contents. An MH10 contains a pair of 'controllers', with the controller used for any particular cycle selected by [[address]] bit 20.

It was a [[multi-port memory]], with 8 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.

It connected to the so-called external memory bus of the 18-or 22-bit address form. Each port on each module could be independently set to use 18- or 22-bit addresses, or to be disabled. The base address of an MH10 is switch-selectable; that address is used on all the ports, unlike the earlier [[PDP-10 memories]].

The MH10 supports two-way [[interleaving]] internally to an MH10, and four-way interleaving between a pair of MH10's (provided they are equally sized); any interleaving applies to all ports. For the two-way case, address bits 20 and 35 are exchanged, so that all even addresses are handled by controller 0, and odd by controller 1.

[[Category: PDP-10 memories]]

@@ Line 1: / Line 1: @@
 The '''MH10''' was a [[core memory|core]] [[main memory]] system for the [[PDP-10]]s, principally the [[KI10]] and early [[KL10]]s. An MH10 could contain up to four 64KW memory banks<sup>*</sup>, for a maximum of 256KW (only 1, 2 or 4 bank operation is supported, however). The [[access time]] is .74 µseconds, and the [[cycle time]] is 1.18 µseconds; [[parity]] is provided to protect the memory contents. An MH10 contains a pair of 'controllers', with the controller used for any particular cycle selected by [[address]] bit 20.
-It was a [[multi-port memory]], with 8 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by  [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
+It was a [[multi-port memory]], with 8 ports per memory system: the [[Central Processing Unit|CPU]] uses at least one port (in a [[multi-processor]] system, at least one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
 It connected to the so-called [[PDP-10 Memory Bus|external memory bus]] of the KA (18-bit address) or KI (22-bit address) form. Each port could be independently set to use 18- or 22-bit addresses, or to be disabled. Banks could also be independently enabled/disabled. The base address of an MH10 is switch-selectable; that address is used on all the ports, unlike the earlier [[PDP-10 memories]].

@@ Line 5: / Line 5: @@
 It connected to the so-called [[PDP-10 Memory Bus|external memory bus]] of the KA (18-bit address) or KI (22-bit address) form. Each port could be independently set to use 18- or 22-bit addresses, or to be disabled. Banks could also be independently enabled/disabled. The base address of an MH10 is switch-selectable; that address is used on all the ports, unlike the earlier [[PDP-10 memories]].
-The MH10 supports two-way [[interleaving]] internally to an MH10, and four-way interleaving between a pair of MH10's (provided they are equally sized); any interleaving applies to all ports. For the two-way case, address bits 20 and 35 are exchanged (recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit), so that all even addresses are handled by controller 0, and odd by controller 1.
+The MH10 supports two-way [[memory interleaving|interleaving]] internally to an MH10, and four-way interleaving between a pair of MH10's (provided they are equally sized); any interleaving applies to all ports. For the two-way case, address bits 20 and 35 are exchanged (recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit), so that all even addresses are handled by controller 0, and odd by controller 1.
 The MH10 shares components with the [[MM11-W core memory]] of the [[PDP-11]]: the G116 sense/inhibit and G236 XY Drive cards; and the H224-B core plane of the MG10 is a 19-bit version of the 18-/16-bit H224-C/D of the MM11-U.

@@ Line 3: / Line 3: @@
 It was a [[multi-port memory]], with 8 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by  [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
-It connected to the so-called external memory bus of the KA (18-bit address) or KI (22-bit address) form. Each port could be independently set to use 18- or 22-bit addresses, or to be disabled. Banks could also be independently enabled/disabled. The base address of an MH10 is switch-selectable; that address is used on all the ports, unlike the earlier [[PDP-10 memories]].
+It connected to the so-called [[PDP-10 Memory Bus|external memory bus]] of the KA (18-bit address) or KI (22-bit address) form. Each port could be independently set to use 18- or 22-bit addresses, or to be disabled. Banks could also be independently enabled/disabled. The base address of an MH10 is switch-selectable; that address is used on all the ports, unlike the earlier [[PDP-10 memories]].
 The MH10 supports two-way [[interleaving]] internally to an MH10, and four-way interleaving between a pair of MH10's (provided they are equally sized); any interleaving applies to all ports. For the two-way case, address bits 20 and 35 are exchanged (recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit), so that all even addresses are handled by controller 0, and odd by controller 1.

← Older revision		Revision as of 11:27, 23 April 2022
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	* [http://www.bitsavers.org/pdf/dec/pdp10/memory/MP00178_MH10_Schematic_Aug76.pdf MH10 Field Maintenance Print Set] (MP00178)		* [http://www.bitsavers.org/pdf/dec/pdp10/memory/MP00178_MH10_Schematic_Aug76.pdf MH10 Field Maintenance Print Set] (MP00178)

−	[[Category: PDP-10 ~~memories~~]]	+	[[Category: PDP-10 Memories]]

← Older revision		Revision as of 03:39, 22 October 2021
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	The MH10 supports two-way [[interleaving]] internally to an MH10, and four-way interleaving between a pair of MH10's (provided they are equally sized); any interleaving applies to all ports. For the two-way case, address bits 20 and 35 are exchanged (recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit), so that all even addresses are handled by controller 0, and odd by controller 1.		The MH10 supports two-way [[interleaving]] internally to an MH10, and four-way interleaving between a pair of MH10's (provided they are equally sized); any interleaving applies to all ports. For the two-way case, address bits 20 and 35 are exchanged (recall that the PDP-10 uses [[big-endian]] numbering, so bit 35 is the low-order bit), so that all even addresses are handled by controller 0, and odd by controller 1.
		+
		+	The MH10 shares components with the [[MM11-W core memory]] of the [[PDP-11]]: the G116 sense/inhibit and G236 XY Drive cards; and the H224-B core plane of the MG10 is a 19-bit version of the 18-/16-bit H224-C/D of the MM11-U.

	<nowiki>*</nowiki> - <i>DEC documentation conflicts on this; the 'MH10 Maintenance Manual', EK-MH10-MM-003, August 1977, says optionally four 64KW banks (pg. 1-1) - and has generally been followed for this writeup; the 'DECsystem-10 DECSYSTEM-20 Processor Reference Manual', AA-H391A-TK, July 1980, says two 128KW banks (pg. G-18).</i>		<nowiki>*</nowiki> - <i>DEC documentation conflicts on this; the 'MH10 Maintenance Manual', EK-MH10-MM-003, August 1977, says optionally four 64KW banks (pg. 1-1) - and has generally been followed for this writeup; the 'DECsystem-10 DECSYSTEM-20 Processor Reference Manual', AA-H391A-TK, July 1980, says two 128KW banks (pg. G-18).</i>

← Older revision		Revision as of 19:53, 17 October 2021
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	* [[MG10 core memory]]		* [[MG10 core memory]]
		+
		+	==External links==
		+
		+	* [http://www.bitsavers.org/pdf/dec/pdp10/memory/EK-MH10-MM-003_MH10_Maint_Aug77.pdf MH10 Maintenance Manual] (EK-MH10-MM-003)
		+	* [http://www.bitsavers.org/pdf/dec/pdp10/memory/MP00178_MH10_Schematic_Aug76.pdf MH10 Field Maintenance Print Set] (MP00178)

	[[Category: PDP-10 memories]]		[[Category: PDP-10 memories]]

@@ Line 1: / Line 1: @@
-The '''MH10''' was a [[core memory|core]] [[main memory]] system for the [[PDP-10]]s, principally the early [[KL10]]. An MG10 could contain up to four 64KW memory banks, for a maximum of 256KW (only 1, 2 or 4 bank operation is supported, however). The [[access time]] is .74 µseconds, and the [[cycle time]] is 1.18 µseconds; [[parity]] is provided to protect the memory contents. An MH10 contains a pair of 'controllers', with the controller used for any particular cycle selected by [[address]] bit 20.
+The '''MH10''' was a [[core memory|core]] [[main memory]] system for the [[PDP-10]]s, principally the early [[KL10]]. An MH10 could contain up to four 64KW memory banks<sup>*</sup>, for a maximum of 256KW (only 1, 2 or 4 bank operation is supported, however). The [[access time]] is .74 µseconds, and the [[cycle time]] is 1.18 µseconds; [[parity]] is provided to protect the memory contents. An MH10 contains a pair of 'controllers', with the controller used for any particular cycle selected by [[address]] bit 20.
 It was a [[multi-port memory]], with 8 ports per memory system: the [[Central Processing Unit|CPU]] uses one port (in a [[multi-processor]] system, one per CPU); the others are used by  [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
@@ Line 6: / Line 6: @@
 The MH10 supports two-way [[interleaving]] internally to an MH10, and four-way interleaving between a pair of MH10's (provided they are equally sized); any interleaving applies to all ports. For the two-way case, address bits 20 and 35 are exchanged, so that all even addresses are handled by controller 0, and odd by controller 1.
 [[Category: PDP-10 memories]]