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2018-10-20T00:35:43Z

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Tor: Added MIPS R4000 CPU page

2014-02-01T15:29:48Z

Added MIPS R4000 CPU page

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{{Infobox CPU
| name = R4000
| manufacturer = [[MIPS Technologies]]
| family = MIPS III
| architecture = 64-bit
| address bus = 64-bit (virtual, only 40 bits used), 36-bit (physical)
| data bus = 64-bit
| year introduced = 1991
| cache = 8KB L1 icache, 8KB L1 dcache
| registers = 64, plus special registers
| clock speed = 100MHz (internal)
| pipeline depth = 8
| instructions = 232 (approximately)
}}

The R4000 processor was launched as the "first true 64-bit RISC microprocessor" [http://www.cbronline.com/news/mips_previews_the_r4000_claims_it_to_be_the_first_true_64_bit_risc_microprocessor]
in 1991. It was developed by [[MIPS Computer Systems]] Inc but soon after (1992) the company was acquired by [[Silicon Graphics]] (SGI)
to secure the supply of MIPS microprocessors and the company was thereafter known as [[MIPS Technologies]].

The processor has on-die [[FPU]] and [[TLB]] and two 64-bit wide register files with 32 entries each, one register file for 32 general purpose registers (although only 31 registers are true registers as R0 is always zero), and one for 32 floating point registers.

The processor can operate in 32-bit or 64-bit mode. In 32-bit mode the CPU registers are 32 bits wide. Instructions are always single 32-bit words and must be word aligned. In 64-bit mode, 32-bit instruction ''operands'' must be sign-extended to 64 bits or results will be unpredictable. Note that this implies that addresses in 32-bit mode are also signed, which limits the virtual memory space to 2GB for 32-bit mode. 64-bit mode can address 1TB (see infobox: Only 40 bits are used for virtual address bits).

The R4000 exists in three variants: R4000PC, R4000SC, and R4000MC. The R4000PC has level 1 cache only. The R4000SC supports an external L2 (or secondary) cache of various capacities from 128KB to 4MB. The secondary cache is accessed through a 128-bit cache data bus. The R4000MC CPU variant is similar to the R4000SC but with additional cache coherency support needed by multiprocessor architectures.

The internal 100MHz clock is derived from an external, lower clock frequency, typically 50MHz.

The CPU can operate in either big-endian or little-endian mode by setting a LE/BE bit in the status register. It can only be set at reset time.

Note that although R4000 is defined as part of the MIPS III family, the Instruction Set Architecture (ISA) is called MIPS2. The next ISA is called MIPS3 and was introduced in the [[R4400]] CPU.

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 Note that although R4000 is defined as part of the MIPS III family, the Instruction Set Architecture (ISA) is called MIPS2. The next ISA is called MIPS3 and was introduced in the [[R4400]] CPU.
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MIPS R4000 - Revision history

Jnc: Proper cat

Tor: Added MIPS R4000 CPU page