MM11-D core memory - Revision history

Jnc: interleaving cleanup

2023-07-30T17:54:53Z

interleaving cleanup

Jnc: +link

2022-06-03T15:42:16Z

+link

Jnc: /* External links */ +FMPS, manuals

2022-04-01T22:40:31Z

‎External links: +FMPS, manuals

Jnc: +img

2021-10-07T11:43:19Z

+img

Jnc: +cat

2018-12-16T15:19:47Z

+cat

Jnc: More appropriate term/link

2018-07-16T01:51:51Z

More appropriate term/link

Jnc: avoid redir

2017-12-17T00:03:31Z

avoid redir

Jnc: Jnc moved page MM11-D to MM11-D core memory: Use standard naming scheme

2017-07-23T15:01:25Z

Jnc moved page MM11-D to MM11-D core memory: Use standard naming scheme

Jnc: Note that it takes two slots worth of space

2017-07-23T14:15:54Z

Note that it takes two slots worth of space

Jnc: A start - gives jumper locations

2017-07-10T06:03:35Z

A start - gives jumper locations

New page

The '''MM11-D''' was a 32 Kbyte [[core memory|core]] [[main memory]] for the early [[PDP-11]] [[UNIBUS]] machines. An MM11-D was composed of two [[hex]] boards, one piggy-backed on the other, and the pair taking only a single [[backplane]] slot:

* An H222-A daughter-board containing the cores
* A G652 mother-board containing most of the electronics, and the contact fingers for plugging into a [[backplane]].

The MM11-D did not use a custom backplane; it plugged into a standard [[Modified UNIBUS Device|MUD slot]]. It is possible to [[interleave]] a pair of MM11-D's to provide reduced effective [[cycle time]]s.

There was also a parity-capable variant, the '''MM11-DP''', which uses an M7850 parity controller plugged into the same backplane as the MM11-D, and substituted a core array with two more bits per word.

==Configuration==

The DEC manuals for the MM11-D list the jumpers used to configure the MM11-D, but they do not show their location, and the board does not contain captions for the jumpers.

They are on the G652 board, on the center right (with the board upright, with the contact fingers at the bottom). W1 is the jumper on the right (toward the edge of the board), and W8 is the one on the left (toward the center of the board), with the others in order between them.

{{PDP-11}}

@@ Line 10: / Line 10: @@
 There was also a parity-capable variant, the '''MM11-DP''', which used an [[M7850 parity controller]] plugged into the same backplane as the MM11-D, and substituted a core array with two more bits per word.
-It is possible to [[interleaving|interleave]] a pair of MM11-D's to provide reduced effective average [[access time]]s.
+It is possible to [[memory interleaving|interleave]] a pair of MM11-D's to provide reduced effective average [[access time]]s.
 ==Configuration==

@@ Line 3: / Line 3: @@
 The '''MM11-D''' was a 32 Kbyte [[core memory|core]] [[main memory]] for [[PDP-11]] [[UNIBUS]] machines. An MM11-D was composed of two [[DEC card form factor‎|hex]] boards, one piggy-backed on the other, and the pair taking only a single [[backplane]] slot (electrically):
-* An H222-A daughter-board containing the cores
+* An H222-A [[daughter-board]] containing the cores
 * A G652 mother-board containing most of the electronics, and the contact fingers for plugging into a [[backplane]] slot

@@ Line 8: / Line 8: @@
 The MM11-D did not use a custom backplane; it plugged into a standard [[Modified UNIBUS Device|MUD slot]]. The pair was 'thick' enough that a normal board cannot be plugged into the next slot; instead, a [[G727 grant continuity card]] must be used there (since it has no components on it, it just clears the H222-A card).
-There was also a parity-capable variant, the '''MM11-DP''', which used an M7850  parity controller plugged into the same backplane as the MM11-D, and substituted a core array with two more bits per word.
+There was also a parity-capable variant, the '''MM11-DP''', which used an [[M7850 parity controller]] plugged into the same backplane as the MM11-D, and substituted a core array with two more bits per word.
 It is possible to [[interleaving|interleave]] a pair of MM11-D's to provide reduced effective average [[access time]]s.
@@ Line 18: / Line 18: @@
 They are on the G652 board, on the center right (with the board upright, with the contact fingers at the bottom). W1 is the jumper on the right (toward the edge of the board), and W8 is the one on the left (toward the center of the board), with the others in order between them.
-{{PDP-11}}
+==External links==
 [[Category: UNIBUS Memories]]

@@ Line 1: / Line 1: @@
-The '''MM11-D''' was a 32 Kbyte [[core memory|core]] [[main memory]] for the early [[PDP-11]] [[UNIBUS]] machines. An MM11-D was composed of two [[DEC card form factor‎|hex]] boards, one piggy-backed on the other, and the pair taking only a single [[backplane]] slot (electrically):
+[[Image:MM11-DFront.jpg|350px|thumb|right|MM11-D set, showing the G652 mother-board]]
 * An H222-A daughter-board containing the cores
-* A G652 mother-board containing most of the electronics, and the contact fingers for plugging into a [[backplane]].
+* A G652 mother-board containing most of the electronics, and the contact fingers for plugging into a [[backplane]] slot
 The MM11-D did not use a custom backplane; it plugged into a standard [[Modified UNIBUS Device|MUD slot]]. The pair was 'thick' enough that a normal board cannot be plugged into the next slot; instead, a [[G727 grant continuity card]] must be used there (since it has no components on it, it just clears the H222-A card).
-There was also a parity-capable variant, the '''MM11-DP''', which uses an M7850  parity controller plugged into the same backplane as the MM11-D, and substituted a core array with two more bits per word.
+There was also a parity-capable variant, the '''MM11-DP''', which used an M7850  parity controller plugged into the same backplane as the MM11-D, and substituted a core array with two more bits per word.
-It is possible to [[interleave]] a pair of MM11-D's to provide reduced effective average [[access time]]s.
+It is possible to [[interleaving|interleave]] a pair of MM11-D's to provide reduced effective average [[access time]]s.
 ==Configuration==

← Older revision		Revision as of 15:19, 16 December 2018
Line 17:		Line 17:

	{{PDP-11}}		{{PDP-11}}
		+
		+	[[Category: UNIBUS Memories]]

← Older revision		Revision as of 00:03, 17 December 2017
Line 1:		Line 1:
−	The '''MM11-D''' was a 32 Kbyte [[core memory\|core]] [[main memory]] for the early [[PDP-11]] [[UNIBUS]] machines. An MM11-D was composed of two [[hex]] boards, one piggy-backed on the other, and the pair taking only a single [[backplane]] slot (electrically):	+	The '''MM11-D''' was a 32 Kbyte [[core memory\|core]] [[main memory]] for the early [[PDP-11]] [[UNIBUS]] machines. An MM11-D was composed of two [[DEC card form factor‎\|hex]] boards, one piggy-backed on the other, and the pair taking only a single [[backplane]] slot (electrically):

	* An H222-A daughter-board containing the cores		* An H222-A daughter-board containing the cores

← Older revision	Revision as of 15:01, 23 July 2017
(No difference)