MM11-L core memory - Revision history

Jnc: /* External links */ +ME11/MF11 prints

2022-03-25T05:14:41Z

‎External links: +ME11/MF11 prints

Jnc: /* External links */ +ME11-L core memory system manual

2021-11-19T22:31:05Z

‎External links: +ME11-L core memory system manual

Jnc: boards shared with MF10

2021-10-22T03:57:12Z

boards shared with MF10

Jnc: /* External links */ +Manual, eng drw

2021-10-16T11:12:14Z

‎External links: +Manual, eng drw

Jnc: +images

2020-10-22T15:54:00Z

+images

Jnc: new article

2020-06-12T13:46:18Z

new article

Jnc: +images

2020-06-12T13:36:21Z

+images

Jnc: G109/110 differences; copyedit fir clarity

2019-12-16T04:06:10Z

G109/110 differences; copyedit fir clarity

Jnc: ooops

2019-07-21T12:55:31Z

ooops

Jnc: ECO potential

2019-07-20T19:24:06Z

ECO potential

@@ Line 64: / Line 64: @@
 * [http://shop-pdp.net/~stuff/PDFs/DEC/DEC-11-HMELA-B-D_ME11-L_Core_Memory_System_Manual.pdf ME11-L core memory system manual] (DEC-11-HMELA-B-D)
-* [http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-11-HMFLA-C-D%20MM11-S,%20MF11-L,%20and%20MF11-LP%20core%20memory%20systems.pdf MM11-S, MF11-L, and MF11-LP core memory systems]
+* [http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-11-HMFLA-C-D%20MM11-S,%20MF11-L,%20and%20MF11-LP%20core%20memory%20systems.pdf MM11-S, MF11-L, and MF11-LP core memory systems] (DEC-11-HMFLA-C-D)
 * [http://bitsavers.org/pdf/dec/pdp11/1105/1105_RevAH_Engineering_Drawings_Jul76.pdf PDP-11/05 Engineering Drawings] - contains complete engineering drawings for the MM11-L board set on pp. 115-137
 [[Category: UNIBUS Memories]]

@@ Line 63: / Line 63: @@
 ==External links==
 * [http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-11-HMFLA-C-D%20MM11-S,%20MF11-L,%20and%20MF11-LP%20core%20memory%20systems.pdf MM11-S, MF11-L, and MF11-LP core memory systems]
 * [http://bitsavers.org/pdf/dec/pdp11/1105/1105_RevAH_Engineering_Drawings_Jul76.pdf PDP-11/05 Engineering Drawings] - contains complete engineering drawings for the MM11-L board set on pp. 115-137
 [[Category: UNIBUS Memories]]

@@ Line 10: / Line 10: @@
 The '''MM11-S''' was a four-slot backplane plus a single MM11-L board set. The '''MF11-L''' was a nine-slot backplane plus a single MM11-L board set; the backplane has room for two more MM11-L board sets. The '''ME11-L''' was an MF11-L in a 5-1/4" rack-mount box, with [[power supply]] (the -LA was wired for 115V supply, the -LB for 230V).
 ==Parity==
@@ Line 15: / Line 17: @@
 [[Image:H215-core-memory-board.jpg|thumb|250px|right|H215 parity core memory board]]
-There was also a [[parity]] variant, the '''MM11-LP'''; parity versions (denoted by a 'P' suffix) were available for all of the above. The MM11-LP added a dual-width [[M7259 Parity Control Module]], and substituted an H215 (with two more bits per word) for the H214, and a G109 for the G110. (The G109 and G110 use the same [[etch]]; the G110 omits the components for the two parity bits.) Enabling parity increased the [[access time]] from 400 nsec to 525 nsec.
+There was also a [[parity]] variant of the MM11-L, the '''MM11-LP'''; parity versions (denoted by a 'P' suffix) were available for all of the above. The MM11-LP added a dual-width [[M7259 Parity Control Module]], and substituted an H215 (with two more bits per word - for byte parity) for the H214, and a G109 for the G110. (The G109 and G110 use the same [[etch]]; the G110 omits the components for the two parity bits.) Enabling parity increased the [[access time]] from 400 nsec to 525 nsec.
-The manual indicates that an 'MF11-LP backplane' was required, but it is not stated if this version had a different [[printed circuit board|PCB]], or if the non-parity version simply had a [[jumper]], like the [[MM11-U core memory]]. After some investigation, apparently there were two versions of the backplane, the early one (part #5409959) which cannot run parity, and a later one (part #5410331) which can. An example of the later backplane had the same jumper as that called for for the MM11-U, from pin 1BU1 to 2BU1; this jumper should not be present for parity memory.
+The manual indicates that an 'MF11-LP backplane' was required, but it is not stated if this version had a different [[printed circuit board|PCB]], or if the non-parity version simply had a [[jumper]], like the [[MM11-U core memory]]. After some investigation, apparently there were two versions of the backplane, the early one ([[DEC part number]] 54-09959) which cannot run parity, and a later one (part number 54-10331) which can. An example of the later backplane had the same jumper as that called for for the MM11-U, from pin 1BU1 to 2BU1; this jumper should not be present for parity memory.
 The parity controller, if present, can only be placed in slot 6. The backplane connects together all the BU1 SSYN pins on the interior slots (2-8), effectively an 'internal' SSYN; the jumper connects together that line, and the main UNIBUS SSYN. The G109/G110 modules drive that 'internal' SSYN; hence the need to install the jumper for non-parity memory. When parity is enabled, the parity controller drives the bus SSYN via pin BV2 in its slot, which is directly connected to bus SSYN via a [[trace]]; the controller uses the 'internal' SSYN as input.

@@ Line 7: / Line 7: @@
 * H214 - quad-width core stack
-The MM11-L required a custom [[backplane]], although some [[Central Processing Unit|CPU]]'s (e.g. the [[PDP-11/05]]) had processor backplanes wired to hold one or more MM11-L sets, in addition to the CPU.
+The MM11-L required a custom [[backplane]], although some [[Central Processing Unit|CPU]]'s (e.g. the [[PDP-11/05]]) had processor backplanes wired to hold one or more MM11-L sets, in addition to the [[Central Processing Unit|CPU]].
 The '''MM11-S''' was a four-slot backplane plus a single MM11-L board set. The '''MF11-L''' was a nine-slot backplane plus a single MM11-L board set; the backplane has room for two more MM11-L board sets. The '''ME11-L''' was an MF11-L in a 5-1/4" rack-mount box, with [[power supply]] (the -LA was wired for 115V supply, the -LB for 230V).
@@ Line 57: / Line 57: @@
 ==See also==
-*[[MM11-K core memory]]
+* [[MM11-K core memory]]
 [[Category: UNIBUS Memories]]

@@ Line 1: / Line 1: @@
 The '''MM11-L core memory''' was a popular, and common, 16 Kbyte [[core memory|core]] [[main memory]] unit for the early [[PDP-11]] [[UNIBUS]] machines. An MM11-L was composed of a three board set:
 * G110 - [[DEC card form factor|hex-width]] memory control logic and data channels
@@ Line 13: / Line 13: @@
 ==Parity==
-[[Image:MM11-L_G110.jpg|thumb|300px|right|G110 control logic board; the blank area in the center right holds the extra components for the parity bits in the G109 variant]]
+[[Image:H215-core-memory-board.jpg|thumb|250px|right|H215 parity core memory board]]
 There was also a [[parity]] variant, the '''MM11-LP'''; parity versions (denoted by a 'P' suffix) were available for all of the above. The MM11-LP added a dual-width [[M7259 Parity Control Module]], and substituted an H215 (with two more bits per word) for the H214, and a G109 for the G110. (The G109 and G110 use the same [[etch]]; the G110 omits the components for the two parity bits.) Enabling parity increased the [[access time]] from 400 nsec to 525 nsec.
@@ Line 54: / Line 54: @@
 The first MM11-L set goes in slots 1/2/3; as MM11-L sets were added, they were installed in slot numerical order. (The location of the parity controller is the only un-used dual slot in a full MF11-L.)
 [[Category: UNIBUS Memories]]

@@ Line 11: / Line 11: @@
 ==Parity==
-There was also a [[parity]] variant, the '''MM11-LP''', which added a dual-width [[M7259 Parity Control Module]], and substituted an H215 (with two more bits per word) for the H214, and a G109 for the G110. Enabling parity increased the [[access time]] from 400 nsec to 525 nsec.
+There was also a [[parity]] variant, the '''MM11-LP'''; parity versions (denoted by a 'P' suffix) were available for all of the above. The MM11-LP added a dual-width [[M7259 Parity Control Module]], and substituted an H215 (with two more bits per word) for the H214, and a G109 for the G110. (The G109 and G110 use the same [[printed circuit board|etch]]; the G110 omits the components for the two parity bits.) Enabling parity increased the [[access time]] from 400 nsec to 525 nsec.
-Parity versions (denoted by a 'P' suffix) were available for all of the above. The manual indicates that an 'MF11-LP backplane' was required, but it is not stated if this version had a different [[printed circuit board|PCB]], or if the non-parity version simply had a [[jumper]], like the [[MM11-U core memory]].
+The manual indicates that an 'MF11-LP backplane' was required, but it is not stated if this version had a different [[printed circuit board|PCB]], or if the non-parity version simply had a [[jumper]], like the [[MM11-U core memory]]. After some investigation, apparently there were two versions of the backplane, the early one (part #5409959) which cannot run parity, and a later one (part #5410331) which can. An example of the later backplane had the same jumper as that called for for the MM11-U, from pin 1BU1 to 2BU1; this jumper should not be present for parity memory.
-After some investigation, apparently there were two versions of the backplane, the early one (part #5409959) which cannot run parity, and a later one (part #5410331) which can. An example of the later backplane had the same jumper as that called for for the MM11-U, from pin 1BU1 to 2BU1. This jumper should not be present for parity memory.
+The parity controller, if present, can only be placed in slot 6. The backplane connects together all the BU1 SSYN pins on the interior slots (2-8), effectively an 'internal' SSYN; the jumper connects together that line, and the main UNIBUS SSYN. The G109/G110 modules drive that 'internal' SSYN; hence the need to install the jumper for non-parity memory. When parity is enabled, the parity controller drives the bus SSYN via pin BV2 in its slot, which is directly connected to bus SSYN via a [[trace]]; the controller uses the 'internal' SSYN as input.
 Note that therefore parity and non-parity memory cannot be mixed on the same backplane. There is also no provision for use of the M7259 parity controller in the PDP-11/05 backplanes which support the MM11-L.
-(One could probably easily [[Engineering Change Order|ECO]] the earlier version to support parity, since the SSYN trace is accessible: cut the trace at 1BU1 and 9BU1, and add the needed [[wire-wrap]] lines.)
+(One could probably easily [[Engineering Change Order|ECO]] the earlier version backplane to support parity, since the SSYN trace is accessible: cut the trace at 1BU1 and 9BU1, and add the needed [[wire-wrap]] lines.)
 ==Module chart==