MM11-U core memory - Revision history

Jnc: boards shared with MG10

2021-10-22T02:53:47Z

boards shared with MG10

Jnc: +imgs

2021-10-17T01:28:21Z

+imgs

Jnc: alt control board version

2021-09-28T11:23:18Z

alt control board version

Jnc: +External links

2021-09-26T16:14:45Z

+External links

Jnc: Add module chart

2019-07-20T04:04:02Z

Add module chart

Jnc: + bplane part #

2019-07-16T19:59:40Z

+ bplane part #

Jnc: +cats, etc

2018-02-22T03:35:56Z

+cats, etc

Jnc: Jnc moved page MM11-U to MM11-U core memory: Use standard naming scheme

2017-07-23T15:04:32Z

Jnc moved page MM11-U to MM11-U core memory: Use standard naming scheme

Jnc: bold MF11-UP as title

2016-03-02T23:23:02Z

bold MF11-UP as title

Jnc: clarify that 11/05 CPU backplane version cannot support parity operation

2016-03-02T23:22:14Z

clarify that 11/05 CPU backplane version cannot support parity operation

@@ Line 14: / Line 14: @@
 The '''MF11-U''' was a backplane plus a single MM11-U board set; the backplane has room for one more MM11-U board set.
-There was also a [[parity]]-capable variant, the '''MM11-UP''', which added an dual-width [[M7259 Parity Control Module]], and substituted an H217-C (with two more bits per word) for the H217-D.
+There was also a [[parity]]-capable variant, the '''MM11-UP''', which added an dual-width [[M7259 Parity Control Module]], and substituted an H217-C (with two more bits per word - for byte parity) for the H217-D.
 It was only available for the MF11-U, not in the CPUs, since it required an extra slot for the M7259 parity controller.
-The board set of the MM11-U (less the M8293) is also used in the [[MJ11 memory system]].
+The board set of the MM11-U (less the M8293) is also used in the [[MJ11 memory system]], and (with the 19-bit wide H217-B variant of the core stack) in the [[MG10 core memory]].
 ==Module chart==

@@ Line 1: / Line 1: @@
 The '''MM11-U''' was a popular, and fairly common, 32 Kbyte [[core memory|core]] [[main memory]] system for the early [[PDP-11]] [[UNIBUS]] machines. An MM11-U was composed of a four board set:
@@ Line 18: / Line 20: @@
 ==Module chart==
 The board organization in the MF11-U backplanes is (viewed from the module side of the backplane):
@@ Line 56: / Line 60: @@
 ==G235 jumpers==
 The MM11-U manual (EK-MF11U-MM-003) describes (pg. 3-12) a set of jumpers (W5-W7) on the G235 card (X and Y selection line current generators - those for the inhibit lines are on the G114) which adjust the bias current for the selection line generators. It goes on to say:

@@ Line 4: / Line 4: @@
 * G235 - hex-width XY Drive, current source, decode module
 * H217-D - hex-width core stack
-* M7293 - quad-width timing and control module
+* M7293/M8293 - quad-width timing and control module
 The MM11-U/UP usually required a custom nine-slot [[backplane]] ([[DEC part number]] 54-10345 or 70-09295), although some [[Central Processing Unit|CPU]]'s (e.g. the [[PDP-11/05]]) had processor backplanes wired to hold an MM11-U set, as well as the CPU set.
@@ Line 13: / Line 15: @@
 It was only available for the MF11-U, not in the CPUs, since it required an extra slot for the M7259 parity controller.
-The board set of the MM11-U (less the M7293) is also used in the [[MJ11 memory system]].
+The board set of the MM11-U (less the M8293) is also used in the [[MJ11 memory system]].
 ==Module chart==
@@ Line 67: / Line 69: @@
 There ''is'' a test to know if the bias current is properly adjusted (see Section 5.3.4, "Drive Current Checks"), and also for the strobe delay (Section 5.3.3, "Sense Strobe Delay Checks"). So in theory, if a G235 card fails one of these tests, it should be possible to change the smallest value jumper, and see if that made things worse or better; and then loop.
-==Board inter-changeability==
+===Board inter-changeability===
 There was some concern that these boards were 'tuned' to be part of a set. E.g. one of the components, in the circuit that the W5-W7 jumpers are part of, is a thermistor on the core stack board (H217). It is not clear if the jumpers are just for dealing with component variations on the G235 board, or if they also include variation elsewhere. In other words, there was a possibility that MM11-U's came as tuned board sets, which should not be 'mixed and matched'.

@@ Line 6: / Line 6: @@
 * M7293 - quad-width timing and control module
-The MM11-U/UP usually required a custom nine-slot [[backplane]] (part #5410345), although some CPU's (e.g. the [[PDP-11/05]]) had processor backplanes wired to hold an MM11-U set, as well as the [[Central Processing Unit|CPU]] set.
+The MM11-U/UP usually required a custom nine-slot [[backplane]] ([[DEC part number]] 54-10345 or 70-09295), although some [[Central Processing Unit|CPU]]'s (e.g. the [[PDP-11/05]]) had processor backplanes wired to hold an MM11-U set, as well as the CPU set.
 The '''MF11-U''' was a backplane plus a single MM11-U board set; the backplane has room for one more MM11-U board set.
@@ Line 12: / Line 12: @@
 There was also a [[parity]]-capable variant, the '''MM11-UP''', which added an dual-width [[M7259 Parity Control Module]], and substituted an H217-C (with two more bits per word) for the H217-D.
 It was only available for the MF11-U, not in the CPUs, since it required an extra slot for the M7259 parity controller.
 ==Module chart==
@@ Line 76: / Line 78: @@
 * [[UNIBUS memories]]
 [[Category: UNIBUS Memories]]

@@ Line 1: / Line 1: @@
-The '''MM11-U''' was a popular, and fairly common, 32 Kbyte [[core memory]] for the early [[PDP-11]] [[UNIBUS]] machines. An MM11-U was composed of a four board set:
+The '''MM11-U''' was a popular, and fairly common, 32 Kbyte [[core memory|core]] [[main memory]] system for the early [[PDP-11]] [[UNIBUS]] machines. An MM11-U was composed of a four board set:
-* G114 - [[DEC card form factor‎|hex-format]] sense/inhibit module
+* G114 - [[DEC card form factor‎|hex-width]] sense/inhibit module
-* G235 - hex-format XY Drive, current source, decode module
+* G235 - hex-width XY Drive, current source, decode module
-* H217-D - hex-format core stack
+* H217-D - hex-width core stack
-* M7293 - quad-format timing and control module
+* M7293 - quad-width timing and control module
-There was also a parity-capable variant, the '''MM11-UP''', which added an M7259 dual-format parity controller, and substituted an H217-C (with two more bits per word) for the H217-D.
+The MM11-U/UP usually required a custom nine-slot [[backplane]] (part #5410345), although some CPU's (e.g. the [[PDP-11/05]]) had processor backplanes wired to hold an MM11-U set, as well as the [[Central Processing Unit|CPU]] set.
-The MM11-U/UP usually required a custom nine-slot [[backplane]] (part #5410345), although some CPU's (e.g. the [[PDP-11/05]]) had processor backplanes wired to hold an MM11-U set as well as the CPU set (but not the -UP, which required an extra slot for the M7259 parity controller).
+The '''MF11-U''' was a backplane plus a single MM11-U board set; the backplane has room for one more MM11-U board set.
-The '''MF11-U''' was a backplane plus a single MM11-U board set; the backplane has room for one more MM11-U board set. The '''MF11-UP''' is the parity version.
+There was also a [[parity]]-capable variant, the '''MM11-UP''', which added an dual-width [[M7259 Parity Control Module]], and substituted an H217-C (with two more bits per word) for the H217-D.
 ==Parity and non-parity backplane configuration==
@@ Line 16: / Line 47: @@
 Installing an MM11-U (non-parity) module set in an MF11-UP backplane will cause the machine to hang when that memory is referenced.
-This is because during parity operation, the SSYN signal is routed through the M7259 Parity Controller board, and that only issues the SSYN once it has checked that the parity is OK. On non-parity installations, the 'proto-SSYN' from the rest of the memory is just hard-wired straight to the output to the UNIBUS.
+This is because during parity operation, the SSYN signal is routed through the M7259 parity controller board, and that only issues the SSYN once it has checked that the parity is OK. On non-parity installations, the 'proto-SSYN' from the rest of the memory is just hard-wired straight to the output to the UNIBUS.
 That requires a jumper on the backplane for non-parity memory: it runs from pin B1U1 to B2U1. This jumper should not be present for parity memory. Note that therefore parity and non-parity memory cannot be mixed on the same backplane.

@@ Line 8: / Line 8: @@
 There was also a parity-capable variant, the '''MM11-UP''', which added an M7259 dual-format parity controller, and substituted an H217-C (with two more bits per word) for the H217-D.
-The MM11-U/UP required a custom backplane, although some CPU's (e.g. the [[PDP-11/05]]) had processor backplanes wired to hold an MM11-U set as well as the CPU (but not the -UP, which required an extra slot for the M7259 parity controller).
+The MM11-U/UP required a custom [[backplane]], although some CPU's (e.g. the [[PDP-11/05]]) had processor backplanes wired to hold an MM11-U set as well as the CPU (but not the -UP, which required an extra slot for the M7259 parity controller).
 The '''MF11-U''' was a nine-slot backplane plus a single MM11-U board set; the backplane has room for one more MM11-U board set. The '''MF11-UP''' is the parity version.
@@ Line 41: / Line 41: @@
 Thus, any 'mixing and matching' that has happened to these boards if they were removed from their machines has probably not caused any problems.

← Older revision	Revision as of 15:04, 23 July 2017
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