MS11-P MOS memory - Revision history

Jnc: /* External links */ + brochure

2023-08-18T15:10:18Z

‎External links: + brochure

Jnc: Formally the MS11-PB

2023-08-08T14:22:28Z

Formally the MS11-PB

Jnc: Avoid dab

2022-09-21T19:18:11Z

Avoid dab

Jnc: /* External links */ bitsavers does have the FMPS

2022-01-16T15:59:46Z

‎External links: bitsavers does have the FMPS

Jnc: /* External links */ +FMPS, manual

2022-01-16T15:57:00Z

‎External links: +FMPS, manual

Jnc: +Image

2020-01-25T18:55:37Z

+Image

Jnc: Timing, power

2020-01-25T16:01:24Z

Timing, power

Jnc: Voltages needed

2020-01-22T13:47:29Z

Voltages needed

Jnc: +cat

2018-10-16T03:34:11Z

+cat

Jnc: A start

2018-07-14T01:12:13Z

A start

New page

The '''MS11-P''' (M8743) is a [[Extended UNIBUS]] [[Dynamic RAM|DRAM]] [[main memory]] card. As an EUB card, it can therefore ''only'' be plugged into the EUB slots on the [[PDP-11/24]] or [[PDP-11/44]] [[backplane]].

It has [[Error-correcting code|ECC]] which automagically corrects single-[[bit]] errors,  and detects double-bit errors.

It is a [[DEC card form factor|hex-height]] card, and holds 1 Mbyte when fully populated with 64Kx1 DRAM [[integrated circuit|chips]]. The memory is arranged as 8 banks, each 16 data bits wide, with 6 additional bits for the ECC.

On power-on, the system is frozen (via negation of the ACLO UNIBUS signal) while the entire memory is cleared, to prevent spurious ECC errors. For [[diagnostic]] purposes, the ECC can be disabled, and there are also means for the CPU to read/write the ECC bits directly.

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 ==External links==
 * [http://bitsavers.org/pdf/dec/pdp11/memory/EK-MS11P-TM-001_Tech_Oct82.pdf MS11-P MOS Memory Technical Manual] (EK-MS11P-TM-001)
 * [http://www.bitsavers.org/pdf/dec/pdp11/memory/MP01477_MS11P_Sep82.pdf MS11-P Field Maintenance Print Set]  (MP01477)
 [[Category: EUB Memories]]

@@ Line 1: / Line 1: @@
 [[Image:MS11-P.jpg|300px|thumb|right|MS11-P board]]
-The '''MS11-P''' is a [[Extended UNIBUS]] [[Metal Oxide Semiconductor|MOS]] [[Dynamic RAM|DRAM]] [[main memory]] card. As an EUB card, it can therefore ''only'' be plugged into the EUB slots on the [[PDP-11/24]] or [[PDP-11/44]] [[backplane]].
+The '''MS11-P''' (formally, the '''MS11-PB'''; if there was an MS11-PA, nothing is now known of it) is a [[Extended UNIBUS]] [[Metal Oxide Semiconductor|MOS]] [[Dynamic RAM|DRAM]] [[main memory]] card. As an EUB card, it can therefore ''only'' be plugged into the EUB slots on the [[PDP-11/24]] or [[PDP-11/44]] [[backplane]].
 It has [[Error-correcting code|ECC]] which automagically corrects single-[[bit]] errors, <!--(at a slight penalty in [[access time|response time]] when an error occurs)--> and detects double-bit errors. On power-on, the system is frozen (via negation of the ACLO UNIBUS signal) while the entire memory is cleared, to prevent spurious ECC errors. For [[diagnostic]] purposes, the ECC can be disabled, and there are also means for the CPU to read/write the ECC bits directly.

@@ Line 5: / Line 5: @@
 It has [[Error-correcting code|ECC]] which automagically corrects single-[[bit]] errors, <!--(at a slight penalty in [[access time|response time]] when an error occurs)--> and detects double-bit errors. On power-on, the system is frozen (via negation of the ACLO UNIBUS signal) while the entire memory is cleared, to prevent spurious ECC errors. For [[diagnostic]] purposes, the ECC can be disabled, and there are also means for the CPU to read/write the ECC bits directly.
-The [[access time]] is 490-535 nsec (read, typical/max; 215-230 nsec extra on error), 100-125 nsec (write); the [[cycle time]] is 680-750 nsec (read cycle) or 580-620 (write cycle). [[Refresh]] time is 675 nsec (typical; 725 nsec maximum), every 11.25-13.75 μsec. <!-- the time for a complete refresh pass is 12.5 μsec (typical), or 13.75 μsec (maximum) -->
+The [[access time]] is 490-535 nsec (read, typical/max; 215-230 nsec extra on error), 100-125 nsec (write); the [[cycle time]] is 680-750 nsec (read cycle) or 580-620 (write cycle). [[Memory refresh]] time is 675 nsec (typical; 725 nsec maximum), every 11.25-13.75 μsec. <!-- the time for a complete refresh pass is 12.5 μsec (typical), or 13.75 μsec (maximum) -->
 It is a [[DEC card form factor|hex-height]] card, the '''M8743''', and holds 1 Mbyte when fully populated with 64Kx1 DRAM [[integrated circuit|chips]]. The memory is arranged as 8 banks, each 16 data bits wide, with 6 additional bits for the ECC.

@@ Line 14: / Line 14: @@
 * [http://bitsavers.org/pdf/dec/pdp11/memory/EK-MS11P-TM-001_Tech_Oct82.pdf MS11-P MOS Memory Technical Manual] (EK-MS11P-TM-001)
-* [https://www.scotnet.co.uk/iain/DEC/memory/MP01477_MS11P_Sep82.pdf MS11-P Field Maintenance Print Set]  (MP01477)
+* [http://www.bitsavers.org/pdf/dec/pdp11/memory/MP01477_MS11P_Sep82.pdf MS11-P Field Maintenance Print Set]  (MP01477)
 [[Category: EUB Memories]]

@@ Line 1: / Line 1: @@
 [[Image:MS11-P.jpg|300px|thumb|right|MS11-P board]]
-The '''MS11-P''' ('''M8743''') is a [[Extended UNIBUS]] [[Metal Oxide Semiconductor|MOS]] [[Dynamic RAM|DRAM]] [[main memory]] card. As an EUB card, it can therefore ''only'' be plugged into the EUB slots on the [[PDP-11/24]] or [[PDP-11/44]] [[backplane]].
+The '''MS11-P''' is a [[Extended UNIBUS]] [[Metal Oxide Semiconductor|MOS]] [[Dynamic RAM|DRAM]] [[main memory]] card. As an EUB card, it can therefore ''only'' be plugged into the EUB slots on the [[PDP-11/24]] or [[PDP-11/44]] [[backplane]].
-It has [[Error-correcting code|ECC]] which automagically corrects single-[[bit]] errors, <!--(at a slight penalty in [[access time|response time]] when an error occurs)--> and detects double-bit errors.
+It has [[Error-correcting code|ECC]] which automagically corrects single-[[bit]] errors, <!--(at a slight penalty in [[access time|response time]] when an error occurs)--> and detects double-bit errors. On power-on, the system is frozen (via negation of the ACLO UNIBUS signal) while the entire memory is cleared, to prevent spurious ECC errors. For [[diagnostic]] purposes, the ECC can be disabled, and there are also means for the CPU to read/write the ECC bits directly.
 The [[access time]] is 490-535 nsec (read, typical/max; 215-230 nsec extra on error), 100-125 nsec (write); the [[cycle time]] is 680-750 nsec (read cycle) or 580-620 (write cycle). [[Refresh]] time is 675 nsec (typical; 725 nsec maximum), every 11.25-13.75 μsec. <!-- the time for a complete refresh pass is 12.5 μsec (typical), or 13.75 μsec (maximum) -->
-On power-on, the system is frozen (via negation of the ACLO UNIBUS signal) while the entire memory is cleared, to prevent spurious ECC errors. For [[diagnostic]] purposes, the ECC can be disabled, and there are also means for the CPU to read/write the ECC bits directly.
+It is a [[DEC card form factor|hex-height]] card, the '''M8743''', and holds 1 Mbyte when fully populated with 64Kx1 DRAM [[integrated circuit|chips]]. The memory is arranged as 8 banks, each 16 data bits wide, with 6 additional bits for the ECC.
 It uses +5V only, unlike the earlier [[MS11-L MOS memory|MS11-L]] and [[MS11-M MOS memory|MS11-M]] MOS memories. The board has provision to use battery backup power to retain data during a power outage. Power requirements are 3.4-4.8A of +5V, and 2.0-2.8A of +5VBB.
 [[Category: EUB Memories]]

← Older revision		Revision as of 18:55, 25 January 2020
Line 1:		Line 1:
		+	[[Image:MS11-P.jpg\|300px\|thumb\|right\|MS11-P board]]
		+
	The '''MS11-P''' ('''M8743''') is a [[Extended UNIBUS]] [[Metal Oxide Semiconductor\|MOS]] [[Dynamic RAM\|DRAM]] [[main memory]] card. As an EUB card, it can therefore ''only'' be plugged into the EUB slots on the [[PDP-11/24]] or [[PDP-11/44]] [[backplane]].		The '''MS11-P''' ('''M8743''') is a [[Extended UNIBUS]] [[Metal Oxide Semiconductor\|MOS]] [[Dynamic RAM\|DRAM]] [[main memory]] card. As an EUB card, it can therefore ''only'' be plugged into the EUB slots on the [[PDP-11/24]] or [[PDP-11/44]] [[backplane]].

← Older revision		Revision as of 03:34, 16 October 2018
Line 6:		Line 6:

	On power-on, the system is frozen (via negation of the ACLO UNIBUS signal) while the entire memory is cleared, to prevent spurious ECC errors. For [[diagnostic]] purposes, the ECC can be disabled, and there are also means for the CPU to read/write the ECC bits directly.		On power-on, the system is frozen (via negation of the ACLO UNIBUS signal) while the entire memory is cleared, to prevent spurious ECC errors. For [[diagnostic]] purposes, the ECC can be disabled, and there are also means for the CPU to read/write the ECC bits directly.
		+
		+	[[Category: EUB Memories]]