MSV11-J memory module - Revision history

Jnc: /* External links */ Bitsavers has reorganized a bit

2026-10-02T15:45:32Z

External links: Bitsavers has reorganized a bit

← Older revision		Revision as of 15:45, 2 October 2026
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	==External links==		==External links==

	* [http://www.bitsavers.org/pdf/dec/qbus/EK-MSV1J-UG_001_May85.pdf MSV11-J MOS Memory User's Guide] (EK-MSV1J-UG-001)		* [http://www.bitsavers.org/pdf/dec/qbus/MSV11-J/EK-MSV1J-UG_001_May85.pdf MSV11-J MOS Memory User's Guide] (EK-MSV1J-UG-001)
	* [http://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/hardware/micronotes/numerical/micronote28.txt MSV11-Q/M/J Memory Comparisons] ([[MicroNote]] #28) - confirms that the -JB/-JC versions will not work reliably on the QBUS		* [http://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/hardware/micronotes/numerical/micronote28.txt MSV11-Q/M/J Memory Comparisons] ([[MicroNote]] #28) - confirms that the -JB/-JC versions will not work reliably on the QBUS
	* [http://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/hardware/micronotes/numerical/micronote30.txt Private Memory Management Between the KDJ11-B and the MSV11-J] (MicroNote #30)		* [http://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/hardware/micronotes/numerical/micronote30.txt Private Memory Management Between the KDJ11-B and the MSV11-J] (MicroNote #30)

Jnc: Link 'MicroNote'

2024-07-24T01:12:58Z

Link 'MicroNote'

← Older revision		Revision as of 01:12, 24 July 2024
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	* [http://www.bitsavers.org/pdf/dec/qbus/EK-MSV1J-UG_001_May85.pdf MSV11-J MOS Memory User's Guide] (EK-MSV1J-UG-001)		* [http://www.bitsavers.org/pdf/dec/qbus/EK-MSV1J-UG_001_May85.pdf MSV11-J MOS Memory User's Guide] (EK-MSV1J-UG-001)
	* [http://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/hardware/micronotes/numerical/micronote28.txt MSV11-Q/M/J Memory Comparisons] (MicroNote 28) - confirms that the -JB/-JC versions will not work reliably on the QBUS		* [http://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/hardware/micronotes/numerical/micronote28.txt MSV11-Q/M/J Memory Comparisons] ([[MicroNote]] #28) - confirms that the -JB/-JC versions will not work reliably on the QBUS
	* [http://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/hardware/micronotes/numerical/micronote30.txt Private Memory Management Between the KDJ11-B and the MSV11-J] (MicroNote 30)		* [http://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/hardware/micronotes/numerical/micronote30.txt Private Memory Management Between the KDJ11-B and the MSV11-J] (MicroNote #30)

	[[Category: QBUS Memories]]		[[Category: QBUS Memories]]
	[[Category: PMI Memories]]		[[Category: PMI Memories]]

Glitch: /* Diagnostics */

2024-07-23T13:00:24Z

Diagnostics

← Older revision		Revision as of 13:00, 23 July 2024
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	The correct [[XXDP]] exerciser is '''VMJAB0''' which is specific to the MSV11-J and fully compatible boards, such as the [[Clearpoint]] [[QED1]]. '''VMSAC0''' should not be used with a MSV11-J.		The correct [[XXDP]] exerciser is '''VMJAB0''' which is specific to the MSV11-J and fully compatible boards, such as the [[Clearpoint]] [[QED1]]. '''VMSAC0''' should not be used with a MSV11-J.

	During exercising with '''VMJAB0''', it is normal for the red ECC error light to ~~illuminate briefly~~. It should not stay on.		During exercising with '''VMJAB0''', it is normal for the red ECC error light to pulse or flicker. It should not stay on.

	[[AK6DN]] diagnostic '''MEMX''' will run correctly on the MSV11-J, but may take longer to expose faults, especially offboard faults that only occur during heavy loading, such as failing KDJ11 cache.		[[AK6DN]] diagnostic '''MEMX''' will run correctly on the MSV11-J, but may take longer to expose faults, especially offboard faults that only occur during heavy loading, such as failing KDJ11 cache.

Glitch: Adding MSV11-J diagnostics information

2024-07-23T12:59:32Z

Adding MSV11-J diagnostics information

← Older revision		Revision as of 12:59, 23 July 2024
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	ASICs on board are 21-24404-01 and 21-22772-01		ASICs on board are 21-24404-01 and 21-22772-01
	</pre>		</pre>

			==Diagnostics==

			The correct [[XXDP]] exerciser is '''VMJAB0''' which is specific to the MSV11-J and fully compatible boards, such as the [[Clearpoint]] [[QED1]]. '''VMSAC0''' should not be used with a MSV11-J.

			During exercising with '''VMJAB0''', it is normal for the red ECC error light to illuminate briefly. It should not stay on.

			[[AK6DN]] diagnostic '''MEMX''' will run correctly on the MSV11-J, but may take longer to expose faults, especially offboard faults that only occur during heavy loading, such as failing KDJ11 cache.

	==See also==		==See also==

Jnc: interleaving cleanup

2023-07-29T22:43:13Z

interleaving cleanup

← Older revision		Revision as of 22:43, 29 July 2023
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	Although it can function in QBUS-only mode (but see the note below about the -JB and -JC versions), it is really intended for use with a PMI-capable [[Central Processing Unit\|CPU]], such as the [[KDJ11-B CPU\|KDJ11-B]]. In systems such as the [[PDP-11/83]], where the primary [[Input/output\|I/O]] [[bus]] is the QBUS, the card 'speaks' PMI to the CPU, and QBUS to the devices. In the [[PDP-11/84]], PMI is used for communication with both the CPU and the devices (via the [[KTJ11-B UNIBUS adapter]]).		Although it can function in QBUS-only mode (but see the note below about the -JB and -JC versions), it is really intended for use with a PMI-capable [[Central Processing Unit\|CPU]], such as the [[KDJ11-B CPU\|KDJ11-B]]. In systems such as the [[PDP-11/83]], where the primary [[Input/output\|I/O]] [[bus]] is the QBUS, the card 'speaks' PMI to the CPU, and QBUS to the devices. In the [[PDP-11/84]], PMI is used for communication with both the CPU and the devices (via the [[KTJ11-B UNIBUS adapter]]).

	The memory is arranged as 2 banks, each 16 data bits wide, with 6 additional bits for the ECC. One bank is used to hold [[word]]s at even word locations, the other for those in odd; the banks are thus [[interleaved]]. A read cycle from the bus will start a read of both sides simultaneously, and so in PMI mode, the second word is already available once the first has been sent.		The memory is arranged as 2 banks, each 16 data bits wide, with 6 additional bits for the ECC. One bank is used to hold [[word]]s at even word locations, the other for those in odd; the banks are thus [[memory interleaving\|interleaved]]. A read cycle from the bus will start a read of both sides simultaneously, and so in PMI mode, the second word is already available once the first has been sent.

	On power-on, the system is frozen (via negation of the BPOK QBUS signal) while the entire memory is cleared, to prevent spurious ECC errors. For [[diagnostic]] purposes, the ECC can be disabled, and there are also means for the CPU to read/write the ECC bits directly.		On power-on, the system is frozen (via negation of the BPOK QBUS signal) while the entire memory is cleared, to prevent spurious ECC errors. For [[diagnostic]] purposes, the ECC can be disabled, and there are also means for the CPU to read/write the ECC bits directly.

Jnc: unote 28 confirms -JB/-JC don't work on QBUS

2022-06-16T17:30:53Z

unote 28 confirms -JB/-JC don't work on QBUS

← Older revision		Revision as of 17:30, 16 June 2022
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	It has [[Error-correcting code\|ECC]] which automagically corrects single-[[bit]] errors (at a slight penalty in [[access time\|response time]] when an error occurs), and detects double-bit errors. It holds 2 Mbytes when fully populated with 256Kx1 DRAM [[integrated circuit\|chips]], or 1 Mbyte when half-populated (the only partially-filled configuration allowed). It supports block mode on both the QBUS and PMI.		It has [[Error-correcting code\|ECC]] which automagically corrects single-[[bit]] errors (at a slight penalty in [[access time\|response time]] when an error occurs), and detects double-bit errors. It holds 2 Mbytes when fully populated with 256Kx1 DRAM [[integrated circuit\|chips]], or 1 Mbyte when half-populated (the only partially-filled configuration allowed). It supports block mode on both the QBUS and PMI.

	Although it can function in QBUS-only mode (but see the note below about the -JB and -JC versions), it is really intended for use with a PMI-capable [[Central Processing Unit\|CPU]], such as the [[KDJ11-B CPU\|KDJ11-B]]. In systems such as the [[PDP-11/83]], where the primary [[Input/output\|I/O]] [[bus]] is the QBUS, the card 'speaks' PMI to the CPU, and QBUS to the devices. In the [[PDP-11/84]], PMI is used for communication with both the CPU and the [[KTJ11-B UNIBUS adapter]].		Although it can function in QBUS-only mode (but see the note below about the -JB and -JC versions), it is really intended for use with a PMI-capable [[Central Processing Unit\|CPU]], such as the [[KDJ11-B CPU\|KDJ11-B]]. In systems such as the [[PDP-11/83]], where the primary [[Input/output\|I/O]] [[bus]] is the QBUS, the card 'speaks' PMI to the CPU, and QBUS to the devices. In the [[PDP-11/84]], PMI is used for communication with both the CPU and the devices (via the [[KTJ11-B UNIBUS adapter]]).

	The memory is arranged as 2 banks, each 16 data bits wide, with 6 additional bits for the ECC. One bank is used to hold [[word]]s at even word locations, the other for those in odd; the banks are thus [[interleaved]]. A read cycle from the bus will start a read of both sides simultaneously, and so in PMI mode, the second word is already available once the first has been sent.		The memory is arranged as 2 banks, each 16 data bits wide, with 6 additional bits for the ECC. One bank is used to hold [[word]]s at even word locations, the other for those in odd; the banks are thus [[interleaved]]. A read cycle from the bus will start a read of both sides simultaneously, and so in PMI mode, the second word is already available once the first has been sent.
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	ASICs on board are 21-24404-01 and 21-22772-01		ASICs on board are 21-24404-01 and 21-22772-01
	</pre>		</pre>
	~~==Further reading==~~

	* ''MSV11-J MOS Memory User's Guide'' ([http://www.bitsavers.org/pdf/dec/qbus/EK-MSV1J-UG_001_May85.pdf EK-MSV1J-UG-001])
	* ''MSV11-Q/M/J Memory Comparisons'' ([http://web.frainresearch.org:8080/projects/pdp-11/micronotes/micronote28.txt MicroNote 28])
	* ''Private Memory Management Between the KDJ11-B and the MSV11-J'' ([http://web.frainresearch.org:8080/projects/pdp-11/micronotes/micronote30.txt MicroNote 30])

	==See also==		==See also==

	* [[MSV11-R memory module]]		* [[MSV11-R memory module]]
			<!--
			==Further reading==
			-->
			==External links==

	~~{{PDP~~-11}}		* [http://www.bitsavers.org/pdf/dec/qbus/EK-MSV1J-UG_001_May85.pdf MSV11-J MOS Memory User's Guide] (EK-MSV1J-UG-001)
			* [http://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/hardware/micronotes/numerical/micronote28.txt MSV11-Q/M/J Memory Comparisons] (MicroNote 28) - confirms that the -JB/-JC versions will not work reliably on the QBUS
			* [http://www.ibiblio.org/pub/academic/computer-science/history/pdp-11/hardware/micronotes/numerical/micronote30.txt Private Memory Management Between the KDJ11-B and the MSV11-J] (MicroNote 30)

	[[Category: QBUS Memories]]		[[Category: QBUS Memories]]
	[[Category: PMI Memories]]		[[Category: PMI Memories]]

Jnc: +Further reading

2021-02-01T01:22:12Z

+Further reading

← Older revision		Revision as of 01:22, 1 February 2021
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	ASICs on board are 21-24404-01 and 21-22772-01		ASICs on board are 21-24404-01 and 21-22772-01
	</pre>		</pre>
			==Further reading==

			* ''MSV11-J MOS Memory User's Guide'' ([http://www.bitsavers.org/pdf/dec/qbus/EK-MSV1J-UG_001_May85.pdf EK-MSV1J-UG-001])
			* ''MSV11-Q/M/J Memory Comparisons'' ([http://web.frainresearch.org:8080/projects/pdp-11/micronotes/micronote28.txt MicroNote 28])
			* ''Private Memory Management Between the KDJ11-B and the MSV11-J'' ([http://web.frainresearch.org:8080/projects/pdp-11/micronotes/micronote30.txt MicroNote 30])

	==See also==		==See also==

Jnc: cat typo

2020-12-14T00:42:00Z

cat typo

← Older revision		Revision as of 00:42, 14 December 2020
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	[[Category: QBUS Memories]]		[[Category: QBUS Memories]]
	[[Category: PMI ~~memories~~]]		[[Category: PMI Memories]]

Jnc: +cat

2020-12-13T23:48:11Z

+cat

← Older revision		Revision as of 23:48, 13 December 2020
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	[[Category: QBUS Memories]]		[[Category: QBUS Memories]]
			[[Category: PMI memories]]

Jnc: Jnc moved page MSV11-J QBUS memory to MSV11-J memory module: Actually PMI mem

2020-10-18T12:03:34Z

Jnc moved page MSV11-J QBUS memory to MSV11-J memory module: Actually PMI mem

← Older revision		Revision as of 12:03, 18 October 2020
(No difference)