MSV11-L MOS Random-Access Memory - Revision history

Vaxorcist: /* Starting address (high) */ fixed typo

2024-08-16T15:03:58Z

‎Starting address (high): fixed typo

Jnc: /* Further reading */ +Differences Between MSVI1-L and MSV11-P Memories

2024-07-25T21:35:50Z

‎Further reading: +Differences Between MSVI1-L and MSV11-P Memories

Jnc: Avoid dab

2022-09-22T12:10:23Z

Avoid dab

Jnc: +jumper diag

2021-12-21T23:06:07Z

+jumper diag

Jnc: Greatly expand; add config info, etc

2021-12-21T17:16:21Z

Greatly expand; add config info, etc

Show changes

Jnc: Pretty simple

2020-05-07T02:14:59Z

Pretty simple

New page

[[Image:MSV11-L.jpg|thumb|250px|right|MSV11-L card]]

The '''MSV11-L''' (M8059) is a [[DEC card form factor|dual]]-height [[QBUS]] [[Dynamic RAM|DRAM]] [[main memory]] card. The MSV11-LK (M8059-Kx) holds 256 KBytes when fully populated with 64K DRAMs [[integrated circuit|chips]], the MSV11-LF (M8059-Fx) is half-populated (the only partially-filled configuration allowed) and holds 128 Kbytes. (The 'x' in the board identifier is a capital letter which identifies the manufacturer of the DRAM chips.)

The memory is arranged as 2 banks, each 16 data bits (1 [[PDP-11]] [[word]]) wide, with 2 additional bits for [[parity]] (1 per [[byte]]). It can be configured as either a [[QBUS#Variable address size|Q18]] card, or a Q22 card.

==Configuration==

The card is configured by [[jumper]]s on [[wire-wrap]] posts; it is possible to set:
* the starting address;
* the size (256KB or 128KB);
* the CSR address;
* parity enable;
* parity error action;
* enable wrong parity;
* bank disable.



==Further reading==

* ''MSV11-L User Guide'', EK-MSV0L-UG
* ''MSV11-L Field Maintenance Printset'' (MP-01238 (M)

{{PDP-11}}

[[Category: QBUS Memories]]

@@ Line 103: / Line 103: @@
 {| class="wikitable"
-! P || N || M || L || Staring Address
+! P || N || M || L || Starting Address
 |-
 | Out || Out || Out || Out || 00000000

← Older revision		Revision as of 21:35, 25 July 2024
Line 215:		Line 215:

	* ''MSV11-L User Guide'', EK-MSV0L-UG (not available online)		* ''MSV11-L User Guide'', EK-MSV0L-UG (not available online)
		+	* ''Differences Between MSVI1-L and MSV11-P Memories'', [[MicroNote]] #111

	==External links==		==External links==

@@ Line 3: / Line 3: @@
 The '''MSV11-L''' is a [[QBUS]] [[DEC card form factor|dual]]-height  [[Dynamic RAM|DRAM]] [[main memory]] card ('''M8059'''). It can be configured as either a [[QBUS#Variable address size|Q18]] card, or a Q22 card<!--; it reportedly supports QBUS block mode-->; it supports [[byte]] [[parity]].
-The memory is arranged as 2 banks, each 16 data bits (one [[PDP-11]] [[word]]) wide. The MSV11-LK (M8059-Kx) holds 256 KBytes when fully populated with 64K DRAM  [[integrated circuit|chips]], the MSV11-LF (M8059-Fx) is half-populated (the only partially-filled configuration allowed) and holds 128 Kbytes. (The 'x' in the board identifier is a capital letter which identifies the manufacturer of the DRAM chips.)
+The memory is arranged as 2 banks, each 16 data bits (one [[PDP-11]] [[word]]) wide. The MSV11-LK (M8059-Kx) holds 256 KBytes when fully populated with 64K DRAM [[integrated circuit|chips]], the MSV11-LF (M8059-Fx) is half-populated (the only partially-filled configuration allowed) and holds 128 Kbytes. (The 'x' in the board identifier is a capital letter which identifies the manufacturer of the DRAM chips.)
-[[Access time]] is 210-230 nsec for reads, and 90-120 nsec for writes; [[cycle time]]s are 560-590 nsec for reads, 605-635 nsec for writes, and 1140-1170 nsec for read/write (DATIO) cycles. [[Refresh]] time (and conflict delay) is 650-685 nsec.
+[[Access time]] is 210-230 nsec for reads, and 90-120 nsec for writes; [[cycle time]]s are 560-590 nsec for reads, 605-635 nsec for writes, and 1140-1170 nsec for read/write (DATIO) cycles. [[Memory refresh]] time (and conflict delay) is 650-685 nsec.
 ==Control and Status Register==
-Each board has a single [[register]], a Control and Status Register, which can be configured in the range 17772100-17772116 (below). In the register contents, all the bits can be read and written by [[software]]; all other than 'Error Address' are cleared by power up and QBUS INIT. Bits which can only be modified by the [[CPU]] are shown in normal font, and those which can also be set by the board [[hardware]] in ''italics''.
+Each board has a single [[register]], a Control and Status Register, which can be configured in the range 17772100-17772116 (below). In the register contents, all the bits can be read and written by [[software]]; all, other than 'Error Address', are cleared by power up and QBUS INIT. Bits which can only be modified by the [[CPU]] are shown in normal font, and those which can also be set by the board [[hardware]] in ''italics''.
 {{16bit-header}}
 | ''Parity Error'' || Extended Error Address Enable || colspan=2 | Unused || colspan=7 | ''Error Address'' || colspan=2 | Unused || Write Wrong Parity || Unused || Parity Error Enable
 {{16bitoctal-bitout}}
-The 'Error Address' field contents depend on the setting of the 'Extended Error Address Enable' bit: when the bit is '0', the field holds the low address (address bits 17 through 11); when the bit is '1', the field holds the high address (address bits 21 through 18 in register bits 8 through 5  - bits 11-9 of the register will still hold address bits 17-15).
+The 'Error Address' field contents depend on the setting of the 'Extended Error Address Enable' bit: when the bit is '0', the field holds the low address (address bits 17 through 11); when the bit is '1', the field holds the high address (address bits 21 through 18 in register bits 8 through 5 - bits 11-9 of the register will still hold address bits 17-15).
 ==Configuration==

@@ Line 9: / Line 9: @@
 ==Control and Status Register==
-Each board has a single [[register]], a Control and Status Register, which can be configured in the range 17772100-17772136 (below). In the register contents, all the bits can be read and written by [[software]]; all other than 'Error Address' are cleared by power up and QBUS INIT. Bits which can only be modified by the [[CPU]] are shown in normal font, and those which can also be set by the board [[hardware]] in ''italics''.
+Each board has a single [[register]], a Control and Status Register, which can be configured in the range 17772100-17772116 (below). In the register contents, all the bits can be read and written by [[software]]; all other than 'Error Address' are cleared by power up and QBUS INIT. Bits which can only be modified by the [[CPU]] are shown in normal font, and those which can also be set by the board [[hardware]] in ''italics''.
 {{16bit-header}}
 | ''Parity Error'' || Extended Error Address Enable || colspan=2 | Unused || colspan=7 | ''Error Address'' || colspan=2 | Unused || Write Wrong Parity || Unused || Parity Error Enable
 {{16bitoctal-bitout}}
-The 'Error Address' field contents depend on the setting of the 'Extended Error Address Enable' bit: when the bit is '0', the field holds the low address (address bits 11 through 17); when the bit is '1', the field holds the high address (address bits 21 through 18 in register bits 8 through 5  - bits 11-9 of the register will still hold address bits 17-15).
+The 'Error Address' field contents depend on the setting of the 'Extended Error Address Enable' bit: when the bit is '0', the field holds the low address (address bits 17 through 11); when the bit is '1', the field holds the high address (address bits 21 through 18 in register bits 8 through 5  - bits 11-9 of the register will still hold address bits 17-15).
 ==Configuration==
 The card is configured by [[wire-wrap]] [[jumper]]s between posts; it is possible to set: