MSV11-M QBUS memory - Revision history

Jnc: rm bloat

2023-07-02T19:25:59Z

rm bloat

Jnc: Jnc moved page MSV11-M memory module to MSV11-M QBUS memory: Actually QBUS mem

2020-10-18T12:07:47Z

Jnc moved page MSV11-M memory module to MSV11-M QBUS memory: Actually QBUS mem

Jnc: + reg jumpers

2020-05-10T12:06:46Z

+ reg jumpers

Jnc: correct caption

2020-05-05T17:22:55Z

correct caption

Jnc: +image

2020-05-05T17:22:02Z

+image

Jnc: All we know

2020-05-05T14:55:24Z

All we know

New page

The '''MSV11-M''' (M7506) is a [[DEC card form factor|dual]]-height [[QBUS]] [[Dynamic RAM|DRAM]] [[main memory]] card. The MSV11-MB (M7506-BA) holds 1 MByte when fully populated with 256K DRAMs [[integrated circuit|chips]], the MSV11-MA (M7506-AA) is half-populated (the only partially-filled configuration allowed) and holds 512 Kbytes.

The memory is arranged as 2 banks, each 16 data bits (1 [[PDP-11]] [[word]]) wide, with 2 additional bits for [[parity]] (1 per [[byte]]). It is a [[QBUS#Variable address size|Q22]] card; it reportedly supports QBUS block mode.

==Configuration==

No documentation on the MSV11-M is extant, so it is currently not known how to configure it.

==Technical information==

As far as is known, there are no copies of the engineering drawings extant for the MSV11-M.


==Further reading==

* ''MSV11-M User Guide'', EK-MSV1M-UG
* ''MSV11-M Field Maintenance Printset'' (MP-02053 - not online)

{{PDP-11}}

[[Category: QBUS Memories]]

← Older revision		Revision as of 17:22, 5 May 2020
Line 1:		Line 1:
−	[[Image:MSV11-M.jpg\|thumb\|250px\|right\|MSV11-M card]]	+	[[Image:MSV11-M.jpg\|thumb\|250px\|right\|MSV11-MB card]]

	The '''MSV11-M''' (M7506) is a [[DEC card form factor\|dual]]-height [[QBUS]] [[Dynamic RAM\|DRAM]] [[main memory]] card. The MSV11-MB (M7506-BA) holds 1 MByte when fully populated with 256K DRAMs [[integrated circuit\|chips]], the MSV11-MA (M7506-AA) is half-populated (the only partially-filled configuration allowed) and holds 512 Kbytes.		The '''MSV11-M''' (M7506) is a [[DEC card form factor\|dual]]-height [[QBUS]] [[Dynamic RAM\|DRAM]] [[main memory]] card. The MSV11-MB (M7506-BA) holds 1 MByte when fully populated with 256K DRAMs [[integrated circuit\|chips]], the MSV11-MA (M7506-AA) is half-populated (the only partially-filled configuration allowed) and holds 512 Kbytes.

← Older revision		Revision as of 17:22, 5 May 2020
Line 1:		Line 1:
−	~~<!--~~ [[Image:MSV11-M.jpg\|thumb\|250px\|right\|MSV11-M card]] ~~-->~~	+	[[Image:MSV11-M.jpg\|thumb\|250px\|right\|MSV11-M card]]
		+
	The '''MSV11-M''' (M7506) is a [[DEC card form factor\|dual]]-height [[QBUS]] [[Dynamic RAM\|DRAM]] [[main memory]] card. The MSV11-MB (M7506-BA) holds 1 MByte when fully populated with 256K DRAMs [[integrated circuit\|chips]], the MSV11-MA (M7506-AA) is half-populated (the only partially-filled configuration allowed) and holds 512 Kbytes.		The '''MSV11-M''' (M7506) is a [[DEC card form factor\|dual]]-height [[QBUS]] [[Dynamic RAM\|DRAM]] [[main memory]] card. The MSV11-MB (M7506-BA) holds 1 MByte when fully populated with 256K DRAMs [[integrated circuit\|chips]], the MSV11-MA (M7506-AA) is half-populated (the only partially-filled configuration allowed) and holds 512 Kbytes.

@@ Line 118: / Line 118: @@
 ==Further reading==
-* ''MSV11-M User Guide'', EK-MSV1M-UG
+* ''MSV11-M User Guide'' (EK-MSV1M-UG - not online)
-* ''MSV11-M Field Maintenance Printset'' (MP-02053 - not online)
+* ''MSV11-M Field Maintenance Print Set'' (MP02053 - not online)
 [[Category: QBUS Memories]]

← Older revision	Revision as of 12:07, 18 October 2020
(No difference)

@@ Line 7: / Line 7: @@
 ==Configuration==
-No documentation on the MSV11-M is extant, so it is currently not known how to configure it.<!-- A single 8-position [[Dual Inline Package|DIP]] switch configures the card:
+No documentation on the MSV11-M is extant, so it is currently not known how to configure it. The purpose of the two-position jumper between E19 (apparently a [[delay line]]) and E18 is currently unknown.
-* Switches S1-S2 select the 22-bit starting address;
+<!-- A single 6-position [[Dual Inline Package|DIP]] switch configures the card's 22-bit starting address:
 * Switches S3-S4 must always be OFF;
 {| class="wikitable"
 ! S1 || S2 || Staring Address
@@ Line 21: / Line 20: @@
 |-
 | ON || ON || 14000000 (3 MB)
-|}
+|} -->
 ==Control Register==
 Each board has a single control [[register]], which can be configured in the range 17772100-17772136.
 {| class="wikitable"
-! S5 !! S6 !! S7 !! S8 !! CSR Address
+! W4 !! W3 !! W2 !! W1 !! CSR Address
 |-
-| ON || ON || ON || ON || 17772100
+| In || In || In || In || 17772100
 |-
-| ON || ON || ON || OFF || 17772102
+| In || In || In || Out || 17772102
 |-
-| ON || ON || OFF || ON || 17772104
+| In || In || Out || In || 17772104
 |-
-| ON || ON || OFF || OFF || 17772106
+| In || In || Out || Out || 17772106
 |-
-| ON || OFF || ON || ON || 17772110
+| In || Out || In || In || 17772110
 |-
-| ON || OFF || ON || OFF || 17772112
+| In || Out || In || Out || 17772112
 |-
-| ON || OFF || OFF || ON || 17772114
+| In || Out || Out || In || 17772114
 |-
-| ON || OFF || OFF || OFF || 17772116
+| In || Out || Out || Out || 17772116
 |-
-| OFF || ON || ON || ON || 17772120
+| Out || In || In || In || 17772120
 |-
-| OFF || ON || ON || OFF || 17772122
+| Out || In || In || Out || 17772122
 |-
-| OFF || ON || OFF || ON || 17772124
+| Out || In || Out || In || 17772124
 |-
-| OFF || ON || OFF || OFF || 17772126
+| Out || In || Out || Out || 17772126
 |-
-| OFF || OFF || ON || ON || 17772130
+| Out || Out || In || In || 17772130
 |-
-| OFF || OFF || ON || OFF || 17772132
+| Out || Out || In || Out || 17772132
 |-
-| OFF || OFF || OFF || ON || 17772134
+| Out || Out || Out || In || 17772134
 |-
-| OFF || OFF || OFF || OFF || 17772136
+| Out || Out || Out || Out || 17772136
 |}
-In the register contents (below), all the bits can be read and written by [[software]]; most are cleared by power up and bus INIT. Bits which can only be modified by the CPU are shown in normal font, and those which can also be set by the [[hardware]] in ''italics''.
+<!--In the register contents (below), all the bits can be read and written by [[software]]; most are cleared by power up and bus INIT. Bits which can only be modified by the CPU are shown in normal font, and those which can also be set by the [[hardware]] in ''italics''.
 {{16bit-header}}
 | ''Parity Error'' || Extended Error Address Enable || colspan=2 | Reserved || colspan=7 | ''Error Address'' || colspan=2 | Reserved || Write Wrong Parity || Reserved || Parity Error Enable