MSV11-Q QBUS memory - Revision history

Jnc: +Config, /* External links */ manuals

2022-03-16T19:25:26Z

+Config, External links: manuals

← Older revision		Revision as of 19:25, 16 March 2022
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	The 'Error Address' field contents depend on the setting of the 'Extended Error Address Enable' bit; when it holds the low address ('Extended Error Address Enable' is 0), it holds address bits 11 through 17; when it holds the high address ('Extended Error Address Enable' is 1), it holds bits 21 through 18 - bits 11-9 of the register are unused.		The 'Error Address' field contents depend on the setting of the 'Extended Error Address Enable' bit; when it holds the low address ('Extended Error Address Enable' is 0), it holds address bits 11 through 17; when it holds the high address ('Extended Error Address Enable' is 1), it holds bits 21 through 18 - bits 11-9 of the register are unused.

			==Configuration==

			The ''MicroPDP-11/53 System Supplement Manual'' (below) has information on how to configure the MSV11-Q, in Section 4.3.1, "MSV11-Q Memory Module".

	==Technical information==		==Technical information==
Line 80:		Line 84:
	==Further reading==		==Further reading==

	* ''MSV11-Q MOS Memory User's Guide'' (EK-MSV1Q-UG-002)
	* ''Microcomputer Products Handbook (1985)'', Chapter 15		* ''Microcomputer Products Handbook (1985)'', Chapter 15
	* ''MSV11-QA, MSV11-QB, and MSV11-QC Field Maintenance ~~Printset~~'' (MP-01931 - not online)		* ''MSV11-QA, MSV11-QB, and MSV11-QC Field Maintenance Print Set'' (MP-01931 - not online)

			==External links==

	~~{{PDP~~-11}}		* [http://www.bitsavers.org/pdf/dec/qbus/EK-MSV1Q-UG-002_MSV11Q_5-85.pdf MSV11-Q MOS Memory User's Guide] (EK-MSV1Q-UG-002)
			* [http://www.bitsavers.org/pdf/dec/pdp11/microPDP11/AZ-GPTAA-MC_MicroPDP11_53_System_Supplement_Jun86.pdf MicroPDP-11/53 System Supplement Manual] (AZ-GPTAA-MC)

	[[Category: QBUS Memories]]		[[Category: QBUS Memories]]

Jnc: /* Technical information */ fmt

2020-03-14T20:13:42Z

Technical information: fmt

← Older revision		Revision as of 20:13, 14 March 2020
Line 27:		Line 27:
	As far as is known, there are no copies of the engineering drawings extant for the MSV11-Q. However, some technical information, enough to [[repairing un-documented MOS memory boards\|repair boards with faulty DRAM chips]], has been gathered on it, and that is made available here.		As far as is known, there are no copies of the engineering drawings extant for the MSV11-Q. However, some technical information, enough to [[repairing un-documented MOS memory boards\|repair boards with faulty DRAM chips]], has been gathered on it, and that is made available here.

	As described above, each board has 8 (sometimes 4) banks in the array of DRAM chips; with 64K chips, each bank is thus 128KB; with 256K chips, they are 512KB. (Note that when writing data, the MSV11-Q sends a 'write' [[signal]] to all the banks, and selects the one to actually use by use of the RAS signal. It's not certain why DEC did this, but since there is no explicit 'read' signal to the chip, and likely the outputs from all the banks are [[wire-OR]]'d together, use of RAS to select the desired bank works for read as well as write.)		As described above, each board has 8 (sometimes 4) banks in the array of DRAM chips; with 64K chips, each bank is thus 128KB; with 256K chips, they are 512KB. (Note that when writing data, the MSV11-Q sends a 'write' [[signal]] to ''all'' the banks, and selects the one to ''actually'' use by use of the RAS signal. It's not certain why DEC did this, but since there is no explicit 'read' signal to the chip, and likely the outputs from all the banks are [[wire-OR]]'d together, use of RAS to select the desired bank works for read as well as write.)

	The chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the top). Bit 0 (value 1) is on the left hand edge of the array; bit 15 (value 0100000) is on the right, with the two parity bits in the middle. The banks run down the board from the metal handle edge; bank 0 is next to the handles, and bank 7 is down near the contact fingers.		The chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the top). Bit 0 (value 1) is on the left hand edge of the array; bit 15 (value 0100000) is on the right, with the two parity bits in the middle. The banks run down the board from the metal handle edge; bank 0 is next to the handles, and bank 7 is down near the contact fingers.

Jnc: /* Technical information */ claridy

2020-03-12T12:03:43Z

Technical information: claridy

← Older revision		Revision as of 12:03, 12 March 2020
Line 27:		Line 27:
	As far as is known, there are no copies of the engineering drawings extant for the MSV11-Q. However, some technical information, enough to [[repairing un-documented MOS memory boards\|repair boards with faulty DRAM chips]], has been gathered on it, and that is made available here.		As far as is known, there are no copies of the engineering drawings extant for the MSV11-Q. However, some technical information, enough to [[repairing un-documented MOS memory boards\|repair boards with faulty DRAM chips]], has been gathered on it, and that is made available here.

	As described above, each board has 8 (sometimes 4) banks in the array of DRAM chips; with 64K chips, each bank is thus 128KB; with 256K chips, they are 512KB. (Note that the MSV11-Q sends a 'write' to all the banks, and selects the one to actually use by use of the RAS signal. It's not certain why DEC did this, but since there is no explicit 'read' signal to the chip, and likely the outputs from all the banks are [[wire-OR]]'d together, use of RAS to select the desired bank works for read as well as write.)		As described above, each board has 8 (sometimes 4) banks in the array of DRAM chips; with 64K chips, each bank is thus 128KB; with 256K chips, they are 512KB. (Note that when writing data, the MSV11-Q sends a 'write' [[signal]] to all the banks, and selects the one to actually use by use of the RAS signal. It's not certain why DEC did this, but since there is no explicit 'read' signal to the chip, and likely the outputs from all the banks are [[wire-OR]]'d together, use of RAS to select the desired bank works for read as well as write.)

	The chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the top). Bit 0 (value 1) is on the left hand edge of the array; bit 15 (value 0100000) is on the right, with the two parity bits in the middle. The banks run down the board from the metal handle edge; bank 0 is next to the handles, and bank 7 is down near the contact fingers.		The chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the top). Bit 0 (value 1) is on the left hand edge of the array; bit 15 (value 0100000) is on the right, with the two parity bits in the middle. The banks run down the board from the metal handle edge; bank 0 is next to the handles, and bank 7 is down near the contact fingers.
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	\|-		\|-
	\| 100000 \|\| E56 \|\| E55 \|\| E54 \|\| E53 \|\| E52 \|\| E51 \|\| E50 \|\| E49		\| 100000 \|\| E56 \|\| E55 \|\| E54 \|\| E53 \|\| E52 \|\| E51 \|\| E50 \|\| E49
	<!-- \|-		<!--\|-
	\| ~~LParity~~ \|\| E		\| Low byte Parity \|\| E
	\|-		\|-
	\| ~~HParity~~ \|\| E -->		\| High byte Parity \|\| E -->
	\|}		\|}

Jnc: dd bit table, more docs

2020-03-10T14:34:45Z

dd bit table, more docs

← Older revision		Revision as of 14:34, 10 March 2020
Line 1:		Line 1:
	[[Image:MSV11-QA.jpg\|thumb\|250px\|right\|MSV11-QA card, later etch]]		[[Image:MSV11-QA.jpg\|thumb\|250px\|right\|MSV11-QA card, later etch]]

	The '''MSV11-Q''' (M7551) is a [[DEC card form factor\|quad]]-height [[QBUS]] [[Dynamic RAM\|DRAM]] [[main memory]] card. Initially it used 64Kx1 DRAM [[integrated circuit\|chips]], later ones ~~uses~~ 256Kx1 DRAMs. The memory is arranged as 8 banks, each 16 data bits (1 [[PDP-11]] [[word]]) wide, with 2 additional bits for [[parity]] (1 per [[byte]]).		The '''MSV11-Q''' (M7551) is a [[DEC card form factor\|quad]]-height [[QBUS]] [[Dynamic RAM\|DRAM]] [[main memory]] card. Initially it used 64Kx1 DRAM [[integrated circuit\|chips]], later ones use 256Kx1 DRAMs. The memory is arranged as 8 banks, each 16 data bits (1 [[PDP-11]] [[word]]) wide, with 2 additional bits for [[parity]] (1 per [[byte]]).

	It holds 1 MByte with 64K DRAMs; 4 Mbytes when fully populated with 256K DRAMs, or 2 Mbytes when half-populated (the only partially-filled configuration allowed). Three versions exist:		It holds 1 MByte with 64K DRAMs; 4 Mbytes when fully populated with 256K DRAMs, or 2 Mbytes when half-populated (the only partially-filled configuration allowed). Three versions exist:
Line 29:		Line 29:
	As described above, each board has 8 (sometimes 4) banks in the array of DRAM chips; with 64K chips, each bank is thus 128KB; with 256K chips, they are 512KB. (Note that the MSV11-Q sends a 'write' to all the banks, and selects the one to actually use by use of the RAS signal. It's not certain why DEC did this, but since there is no explicit 'read' signal to the chip, and likely the outputs from all the banks are [[wire-OR]]'d together, use of RAS to select the desired bank works for read as well as write.)		As described above, each board has 8 (sometimes 4) banks in the array of DRAM chips; with 64K chips, each bank is thus 128KB; with 256K chips, they are 512KB. (Note that the MSV11-Q sends a 'write' to all the banks, and selects the one to actually use by use of the RAS signal. It's not certain why DEC did this, but since there is no explicit 'read' signal to the chip, and likely the outputs from all the banks are [[wire-OR]]'d together, use of RAS to select the desired bank works for read as well as write.)

	The chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the ~~bottom~~). Bit 0 (value 1) is on the ~~right~~ hand edge of the array; bit 15 (value 0100000) is on the ~~left~~, with the two parity bits in the middle. The banks run up the board from the metal handle edge; bank 0 is next to the handles, and bank 7 is up near the contact fingers.		The chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the top). Bit 0 (value 1) is on the left hand edge of the array; bit 15 (value 0100000) is on the right, with the two parity bits in the middle. The banks run down the board from the metal handle edge; bank 0 is next to the handles, and bank 7 is down near the contact fingers.

	~~<!--~~ {\| class="wikitable"		Thus, for example, bit 0 of bank 0 is in chip E197. The full table is:
	! Bit !! ~~Block~~ 0 !! ~~Block~~ 1 !! ~~Block~~ 2 !! ~~Block~~ 3
	\|-		{\| class="wikitable"
	~~\| 01 \|\| R05 \|\| L02 \|\| L010 \|\| R213~~		! Bit !! Bank 0 !! Bank 1 !! Bank 2 !! Bank 3 !! Bank 4 !! Bank 5 !! Bank 6 !! Bank 7
	\|-
	~~\| 02 \|\| R14 \|\| L12 \|\| L110 \|\| R113~~
	\|-
	~~\| 04 \|\| R24 \|\| L22 \|\| L210 \|\| R212~~
	\|-
	~~\| 10 \|\| R04 \|\| L03 \|\| L011 \|\| R012~~
	\|-
	~~\| 20 \|\| R13 \|\| L13 \|\| L111 \|\| R112~~
	\|-		\|-
	\| 40 \|\| ~~R23~~ \|\| ~~L23~~ \|\| ~~L212~~ \|\| ~~R211~~		\| 01 \|\| E197 \|\| E196 \|\| E195 \|\| E194 \|\| E193 \|\| E192 \|\| E191 \|\| E190
	\|-		\|-
	\| ~~100~~ \|\| ~~R03~~ \|\| ~~L04~~ \|\| ~~L012~~ \|\| ~~R111~~		\| 02 \|\| E189 \|\| E188 \|\| E187 \|\| E186 \|\| E185 \|\| E184 \|\| E183 \|\| E182
	\|-		\|-
	\| ~~200~~ \|\| ~~R22~~ \|\| ~~L14~~ \|\| ~~L112~~ \|\| ~~R210~~		\| 04 \|\| E180 \|\| E179 \|\| E178 \|\| E177 \|\| E176 \|\| E175 \|\| E174 \|\| E173
	\|-		\|-
	\| ~~400~~ \|\| ~~R12~~ \|\| ~~L24~~ \|\| ~~L113~~ \|\| ~~R110~~		\| 10 \|\| E172 \|\| E171 \|\| E170 \|\| E170 \|\| E169 \|\| E168 \|\| E167 \|\| E166
	\|-		\|-
	\| ~~1000~~ \|\| ~~R02~~ \|\| ~~L05~~ \|\| ~~L013~~ \|\| ~~R010~~		\| 20 \|\| E164 \|\| E163 \|\| E162 \|\| E161 \|\| E160 \|\| E159 \|\| E158 \|\| E157
	\|-		\|-
	\| ~~2000~~ \|\| ~~R21~~ \|\| ~~L15~~ \|\| ~~L014~~ \|\| ~~R29~~		\| 40 \|\| E155 \|\| E154 \|\| E153 \|\| E152 \|\| E151 \|\| E150 \|\| E149 \|\| E148
	\|-		\|-
	\| ~~4000~~ \|\| ~~R11~~ \|\| ~~L25~~ \|\| ~~L115~~ \|\| ~~R19~~		\| 100 \|\| E147 \|\| E146 \|\| E145 \|\| E144 \|\| E143 \|\| E142 \|\| E141 \|\| E140
	\|-		\|-
	\| ~~10000~~ \|\| ~~R01~~ \|\| ~~L06~~ \|\| ~~L015~~ \|\| ~~R09~~		\| 200 \|\| E139 \|\| E138 \|\| E137 \|\| E136 \|\| E135 \|\| E134 \|\| E133 \|\| E132
	\|-		\|-
	\| ~~20000~~ \|\| ~~R20~~ \|\| ~~L16~~ \|\| ~~L116~~ \|\| ~~R28~~		\| 400 \|\| E114 \|\| E113 \|\| E112 \|\| E111 \|\| E110 \|\| E109 \|\| E108 \|\| E107
	\|-		\|-
	\| ~~40000~~ \|\| ~~R10~~ \|\| ~~L26~~ \|\| ~~L114~~ \|\| ~~R18~~		\| 1000 \|\| E105 \|\| E104 \|\| E103 \|\| E102 \|\| E101 \|\| E100 \|\| E99 \|\| E98
	\|-		\|-
	\| ~~100000~~ \|\| ~~R00~~ \|\| ~~L07~~ \|\| ~~L016~~ \|\| ~~R08~~		\| 2000 \|\| E97 \|\| E96 \|\| E95 \|\| E94 \|\| E93 \|\| E92 \|\| E91 \|\| E90
	\|-		\|-
	\| ~~CBx~~ \|\| ~~R25~~ \|\| ~~L21~~ \|\| ~~L29~~ \|\| ~~R214~~		\| 4000 \|\| E89 \|\| E88 \|\| E87 \|\| E86 \|\| E85 \|\| E84 \|\| E83 \|\| E82
	\|-		\|-
	\| ~~CB0~~ \|\| ~~R27~~ \|\| ~~L00~~ \|\| ~~L08~~ \|\| ~~R216~~		\| 10000 \|\| E81 \|\| E80 \|\| E79 \|\| E78 \|\| E77 \|\| E76 \|\| E75 \|\| E74
	\|-		\|-
	\| ~~CB1~~ \|\| ~~R26~~ \|\| ~~L10~~ \|\| ~~L18~~ \|\| ~~R215~~		\| 20000 \|\| E72 \|\| E71 \|\| E70 \|\| E70 \|\| E69 \|\| E68 \|\| E67 \|\| E66
	\|-		\|-
	\| ~~CB2~~ \|\| ~~R16~~ \|\| ~~L20~~ \|\| ~~L28~~ \|\| ~~R014~~		\| 40000 \|\| E64 \|\| E63 \|\| E62 \|\| E61 \|\| E60 \|\| E59 \|\| E58 \|\| E57
	\|-		\|-
	\| ~~CB4~~ \|\| ~~R06~~ \|\| ~~L01~~ \|\| ~~L09~~ \|\| ~~R013~~		\| 100000 \|\| E56 \|\| E55 \|\| E54 \|\| E53 \|\| E52 \|\| E51 \|\| E50 \|\| E49
			<!-- \|-
			\| LParity \|\| E
	\|-		\|-
	\| ~~CB8~~ \|\| ~~R15 \|\| L11 \|\| L19 \|\| R114~~		\| HParity \|\| E -->
	\|}		\|}

	''Note:'' When a DRAM chip is removed, if the affected memory location is then read, that bit will be ''high'' (1), not ''low'' (0); the affected input (apparently separate pins for the low and high banks) must float to 1 when there is no DRAM chip present to drive the input.		<!-- ''Note:'' When a DRAM chip is removed, if the affected memory location is then read, that bit will be ''high'' (1), not ''low'' (0); the affected input (apparently separate pins for the low and high banks) must float to 1 when there is no DRAM chip present to drive the input. -->
	-->
	The following 64K DRAM chips have been observed to be used: M5K4164ANP-15P (Micron Technologies), NEC D4164C211 (NEC Electronics). <!-- HM50256-15 (Hitachi), TMS4256-15NL (Texas Instruments), MB81256-15 (Fujitsu).		The following 64K DRAM chips have been observed to be used: M5K4164ANP-15P (Micron Technologies), NEC D4164C211 (NEC Electronics). <!-- HM50256-15 (Hitachi), TMS4256-15NL (Texas Instruments), MB81256-15 (Fujitsu).

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	==Further reading==		==Further reading==

	* ''MSV11-QA, MSV11-QB, and MSV11-QC Field Maintenance Printset'' (MP-01931)		* ''MSV11-Q MOS Memory User's Guide'' (EK-MSV1Q-UG-002)
			* ''Microcomputer Products Handbook (1985)'', Chapter 15
			* ''MSV11-QA, MSV11-QB, and MSV11-QC Field Maintenance Printset'' (MP-01931 - not online)

	{{PDP-11}}		{{PDP-11}}

	[[Category: QBUS Memories]]		[[Category: QBUS Memories]]

Jnc: /* Technical information */ clarify

2020-03-09T17:41:35Z

Technical information: clarify

← Older revision		Revision as of 17:41, 9 March 2020
Line 27:		Line 27:
	As far as is known, there are no copies of the engineering drawings extant for the MSV11-Q. However, some technical information, enough to [[repairing un-documented MOS memory boards\|repair boards with faulty DRAM chips]], has been gathered on it, and that is made available here.		As far as is known, there are no copies of the engineering drawings extant for the MSV11-Q. However, some technical information, enough to [[repairing un-documented MOS memory boards\|repair boards with faulty DRAM chips]], has been gathered on it, and that is made available here.

	As described above, each board has 8 (sometimes 4) banks in the array of DRAM chips; with 64K chips, each bank is thus 128KB; with 256K chips, they are 512KB. (Note that the MSV11-Q sends a 'write' to all the banks, and selects the one to actually use by use of the RAS signal. It's not certain why DEC did this, but since there is no 'read' signal, and likely the outputs from all the banks are [[wire-OR]]'d together, use of RAS to select the bank works for read as well as write.)		As described above, each board has 8 (sometimes 4) banks in the array of DRAM chips; with 64K chips, each bank is thus 128KB; with 256K chips, they are 512KB. (Note that the MSV11-Q sends a 'write' to all the banks, and selects the one to actually use by use of the RAS signal. It's not certain why DEC did this, but since there is no explicit 'read' signal to the chip, and likely the outputs from all the banks are [[wire-OR]]'d together, use of RAS to select the desired bank works for read as well as write.)

	The chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the bottom). Bit 0 (value 1) is on the right hand edge of the array; bit 15 (value 0100000) is on the left, with the two parity bits in the middle. The banks run up the board from the metal handle edge; bank 0 is next to the handles, and bank 7 is up near the contact fingers.		The chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the bottom). Bit 0 (value 1) is on the right hand edge of the array; bit 15 (value 0100000) is on the left, with the two parity bits in the middle. The banks run up the board from the metal handle edge; bank 0 is next to the handles, and bank 7 is up near the contact fingers.

Jnc: /* Technical information */ Add bank->chip mapping

2020-03-08T23:09:53Z

Technical information: Add bank->chip mapping

← Older revision		Revision as of 23:09, 8 March 2020
Line 27:		Line 27:
	As far as is known, there are no copies of the engineering drawings extant for the MSV11-Q. However, some technical information, enough to [[repairing un-documented MOS memory boards\|repair boards with faulty DRAM chips]], has been gathered on it, and that is made available here.		As far as is known, there are no copies of the engineering drawings extant for the MSV11-Q. However, some technical information, enough to [[repairing un-documented MOS memory boards\|repair boards with faulty DRAM chips]], has been gathered on it, and that is made available here.

	As described above, each board has 8 (sometimes 4) banks in the array of DRAM chips; with 64K chips, each bank is thus 128KB; with 256K chips, they are 512KB. (Note that the MSV11-Q sends a 'write' to all the banks, and selects the one to actually use by use of the RAS signal. It's not certain why ~~it does~~ this, but since there is no 'read' signal, and likely the outputs from all the banks are [[wire-OR]]'d together, use of RAS to select the bank works for read as well as write.)		As described above, each board has 8 (sometimes 4) banks in the array of DRAM chips; with 64K chips, each bank is thus 128KB; with 256K chips, they are 512KB. (Note that the MSV11-Q sends a 'write' to all the banks, and selects the one to actually use by use of the RAS signal. It's not certain why DEC did this, but since there is no 'read' signal, and likely the outputs from all the banks are [[wire-OR]]'d together, use of RAS to select the bank works for read as well as write.)

	The chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the bottom). Bit 0 (value 1) is on the right hand edge of the array; bit 15 (value 0100000) is on the left, with the two parity bits in the middle.		The chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the bottom). Bit 0 (value 1) is on the right hand edge of the array; bit 15 (value 0100000) is on the left, with the two parity bits in the middle. The banks run up the board from the metal handle edge; bank 0 is next to the handles, and bank 7 is up near the contact fingers.

	<!-- {\| class="wikitable"		<!-- {\| class="wikitable"
Line 79:		Line 79:
	\|}		\|}

	''Note:'' When a DRAM chip is removed, if the affected memory location is then read, that bit will be ''high'' (1), not ''low'' (0); the affected input (apparently separate pins for the low and high banks) must float to 1 when there is no DRAM chip present to drive the input. -->		''Note:'' When a DRAM chip is removed, if the affected memory location is then read, that bit will be ''high'' (1), not ''low'' (0); the affected input (apparently separate pins for the low and high banks) must float to 1 when there is no DRAM chip present to drive the input.
			-->
	The following 64K DRAM chips have been observed to be used: M5K4164ANP-15P (Micron Technologies), NEC D4164C211 (NEC Electronics). <!-- HM50256-15 (Hitachi), TMS4256-15NL (Texas Instruments), MB81256-15 (Fujitsu).		The following 64K DRAM chips have been observed to be used: M5K4164ANP-15P (Micron Technologies), NEC D4164C211 (NEC Electronics). <!-- HM50256-15 (Hitachi), TMS4256-15NL (Texas Instruments), MB81256-15 (Fujitsu).

Jnc: /* Technical information */ RAS kludge

2020-03-08T23:05:09Z

Technical information: RAS kludge

← Older revision		Revision as of 23:05, 8 March 2020
Line 27:		Line 27:
	As far as is known, there are no copies of the engineering drawings extant for the MSV11-Q. However, some technical information, enough to [[repairing un-documented MOS memory boards\|repair boards with faulty DRAM chips]], has been gathered on it, and that is made available here.		As far as is known, there are no copies of the engineering drawings extant for the MSV11-Q. However, some technical information, enough to [[repairing un-documented MOS memory boards\|repair boards with faulty DRAM chips]], has been gathered on it, and that is made available here.

	As described above, each board has 8 (sometimes 4) banks in the array of DRAM chips; with 64K chips, each bank is thus 128KB; with 256K chips, they are 512KB.		As described above, each board has 8 (sometimes 4) banks in the array of DRAM chips; with 64K chips, each bank is thus 128KB; with 256K chips, they are 512KB. (Note that the MSV11-Q sends a 'write' to all the banks, and selects the one to actually use by use of the RAS signal. It's not certain why it does this, but since there is no 'read' signal, and likely the outputs from all the banks are [[wire-OR]]'d together, use of RAS to select the bank works for read as well as write.)

	The chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the bottom). Bit 0 (value 1) is on the right hand edge of the array; bit 15 (value 0100000) is on the left, with the two parity bits in the middle.		The chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the bottom). Bit 0 (value 1) is on the right hand edge of the array; bit 15 (value 0100000) is on the left, with the two parity bits in the middle.

Jnc: /* Technical information */ Bank size

2020-03-08T14:38:11Z

Technical information: Bank size

← Older revision		Revision as of 14:38, 8 March 2020
Line 27:		Line 27:
	As far as is known, there are no copies of the engineering drawings extant for the MSV11-Q. However, some technical information, enough to [[repairing un-documented MOS memory boards\|repair boards with faulty DRAM chips]], has been gathered on it, and that is made available here.		As far as is known, there are no copies of the engineering drawings extant for the MSV11-Q. However, some technical information, enough to [[repairing un-documented MOS memory boards\|repair boards with faulty DRAM chips]], has been gathered on it, and that is made available here.

	As described above, each board has 8 (sometimes 4) banks in the array of DRAM chips; ~~the~~ chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the ~~borrom~~). Bit 0 (value 1) is on the right hand edge of the array; bit 15 (value 0100000) is on the left, with the two parity bits in the middle.		As described above, each board has 8 (sometimes 4) banks in the array of DRAM chips; with 64K chips, each bank is thus 128KB; with 256K chips, they are 512KB.

			The chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the bottom). Bit 0 (value 1) is on the right hand edge of the array; bit 15 (value 0100000) is on the left, with the two parity bits in the middle.

	<!-- {\| class="wikitable"		<!-- {\| class="wikitable"

Jnc: Start adding chip location info

2019-12-12T16:49:54Z

Start adding chip location info

← Older revision		Revision as of 16:49, 12 December 2019
Line 25:		Line 25:
	==Technical information==		==Technical information==

	As far as is known, there are no copies of the engineering drawings extant for the MSV11-Q. ~~<!--~~ However, some technical information, enough to [[repairing un-documented MOS memory boards\|repair boards with faulty DRAM chips]], has been gathered on it, and that is made available here.		As far as is known, there are no copies of the engineering drawings extant for the MSV11-Q. However, some technical information, enough to [[repairing un-documented MOS memory boards\|repair boards with faulty DRAM chips]], has been gathered on it, and that is made available here.

	{\| class="wikitable"		As described above, each board has 8 (sometimes 4) banks in the array of DRAM chips; the chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the borrom). Bit 0 (value 1) is on the right hand edge of the array; bit 15 (value 0100000) is on the left, with the two parity bits in the middle.

			<!-- {\| class="wikitable"
	! Bit !! Block 0 !! Block 1 !! Block 2 !! Block 3		! Bit !! Block 0 !! Block 1 !! Block 2 !! Block 3
	\|-		\|-
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	\|}		\|}

	''Note:'' When a DRAM chip is removed, if the affected memory location is then read, that bit will be ''high'' (1), not ''low'' (0); the affected input (apparently separate pins for the low and high banks) must float to 1 when there is no DRAM chip present to drive the input.		''Note:'' When a DRAM chip is removed, if the affected memory location is then read, that bit will be ''high'' (1), not ''low'' (0); the affected input (apparently separate pins for the low and high banks) must float to 1 when there is no DRAM chip present to drive the input. -->

	The following DRAM chips have been observed to be used: ~~MT1259~~-12 (Micron Technologies), HM50256-15 (Hitachi~~), NEC 41256 (NEC Electronics~~), TMS4256-15NL (Texas Instruments), MB81256-15 (Fujitsu).		The following 64K DRAM chips have been observed to be used: M5K4164ANP-15P (Micron Technologies), NEC D4164C211 (NEC Electronics). <!-- HM50256-15 (Hitachi), TMS4256-15NL (Texas Instruments), MB81256-15 (Fujitsu).

	Note that some of these parts are 120 nsec parts, while others are 150 nsec; the faster parts do not seem to be necessary, or give any advantage. -->		Note that some of these parts are 120 nsec parts, while others are 150 nsec; the faster parts do not seem to be necessary, or give any advantage. -->

Jnc: Add image

2019-11-24T21:08:43Z

Add image

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	~~<!--~~ [[Image:~~M7551~~.jpg\|~~150px~~\|right]] ~~-->~~		[[Image:MSV11-QA.jpg\|thumb\|250px\|right\|MSV11-QA card, later etch]]

	The '''MSV11-Q''' (M7551) is a [[DEC card form factor\|quad]]-height [[QBUS]] [[Dynamic RAM\|DRAM]] [[main memory]] card. Initially it used 64Kx1 DRAM [[integrated circuit\|chips]], later ones uses 256Kx1 DRAMs. The memory is arranged as 8 banks, each 16 data bits (1 [[PDP-11]] [[word]]) wide, with 2 additional bits for [[parity]] (1 per [[byte]]).		The '''MSV11-Q''' (M7551) is a [[DEC card form factor\|quad]]-height [[QBUS]] [[Dynamic RAM\|DRAM]] [[main memory]] card. Initially it used 64Kx1 DRAM [[integrated circuit\|chips]], later ones uses 256Kx1 DRAMs. The memory is arranged as 8 banks, each 16 data bits (1 [[PDP-11]] [[word]]) wide, with 2 additional bits for [[parity]] (1 per [[byte]]).