MSV11-R memory module - Revision history

Jnc: give page nos for eng drw

2021-12-24T13:51:10Z

give page nos for eng drw

Jnc: typo

2020-12-30T22:34:56Z

typo

Jnc: block op details

2020-12-16T17:45:42Z

block op details

Jnc: cat typo

2020-12-14T00:43:15Z

cat typo

Jnc: +cat

2020-12-13T23:47:26Z

+cat

Jnc: Add chip bit table

2020-12-13T22:04:24Z

Add chip bit table

Jnc: prints now available

2020-12-13T20:20:27Z

prints now available

Jnc: Note definitely PMI; +warning

2020-05-06T21:41:41Z

Note definitely PMI; +warning

Jnc: All we know

2020-05-04T22:05:14Z

All we know

New page

[[Image:MSV11-R.jpg|thumb|250px|right|MSV11-R card]]

The '''MSV11-R''' (M7458) is a [[DEC card form factor|quad]]-height [[QBUS]] [[Dynamic RAM|DRAM]] [[main memory]] card. The MSV111-RA (M7358-A) holds 1 MByte when fully populated with 256K DRAMs [[integrated circuit|chips]].

The memory is arranged as 2 banks, each 16 data bits (1 [[PDP-11]] [[word]]) wide, with 2 additional bits for [[parity]] (1 per [[byte]]). It is a [[QBUS#Variable address size|Q22]] card; reportedly it is also a [[Private Memory Interconnect|PMI]] card. 

==Configuration==

A single 8-position [[Dual Inline Package|DIP]] switch configures the card:

* Switches S1-S2 select the 22-bit starting address;
* Switches S3-S4 must always be OFF;
* Switches S5-S8 select the CSR address.

{| class="wikitable"
! S1 || S2 || Staring Address
|-
| OFF || OFF || 00000000 (0 MB)
|-
| OFF || ON || 04000000 (1 MB)
|-
| ON || OFF || 10000000 (2 MB)
|-
| ON || ON || 14000000 (3 MB)
|}

==Control Register==

Each board has a single control [[register]], which can be configured in the range 17772100-17772136.
{| class="wikitable"
! S5 !! S6 !! S7 !! S8 !! CSR Address
|-
| ON || ON || ON || ON || 17772100
|-
| ON || ON || ON || OFF || 17772102
|-
| ON || ON || OFF || ON || 17772104
|-
| ON || ON || OFF || OFF || 17772106
|-
| ON || OFF || ON || ON || 17772110
|-
| ON || OFF || ON || OFF || 17772112
|-
| ON || OFF || OFF || ON || 17772114
|-
| ON || OFF || OFF || OFF || 17772116
|-
| OFF || ON || ON || ON || 17772120
|-
| OFF || ON || ON || OFF || 17772122
|-
| OFF || ON || OFF || ON || 17772124
|-
| OFF || ON || OFF || OFF || 17772126
|-
| OFF || OFF || ON || ON || 17772130
|-
| OFF || OFF || ON || OFF || 17772132
|-
| OFF || OFF || OFF || ON || 17772134
|-
| OFF || OFF || OFF || OFF || 17772136
|}


==Technical information==

As far as is known, there are no copies of the engineering drawings extant for the MSV11-R.

The following 256K DRAM chips have been observed to be used: MB81256-15 (Fujitsu).

==Further reading==

* ''MSV11-R User Guide'', EK-MSV1R-UG


{{PDP-11}}

[[Category: QBUS Memories]]

@@ Line 131: / Line 131: @@
 ==External links==
-* [http://www.bitsavers.org/pdf/dec/pdp11/1184/MP-02015-01_11-84_Maintenance_Print_Set_198412.pdf PDP-11/84 Maintenance Print Set] - Contains MSV11-R engineering drawings
+* [http://www.bitsavers.org/pdf/dec/pdp11/1184/MP-02015-01_11-84_Maintenance_Print_Set_198412.pdf 11/84 Field Maintenance Print Set (MP-02015-001)] - Contains MSV11-R engineering drawings on pp. 29-45
 [[Category: QBUS Memories]]
 [[Category: PMI Memories]]

@@ Line 5: / Line 5: @@
 '''''NOTE:''''' As a PMI card, it uses the [[CD interconnect]]; it can therefore ''only'' be plugged into a [[QBUS#Backplanes|Q/CD backplane]]. Plugging an MSV11-R card into a regular [[QBUS#Backplanes|Q/Q backplane]] will '''damage''' the MSV11-R.
-The MSV111-RA (M7358-A) holds 1 MByte when fully populated with 256K DRAM  [[integrated circuit|chips]]. The memory is arranged as 2 banks, each 16 data bits (1 [[PDP-11]] [[word]]) wide, with 2 additional bits for [[parity]] (1 per [[byte]]). In theory, it could support being half-populated (512 Kbytes), with only one bank; there is a jumper, W1, which seems to support this configuration, but no documentation for it. It is not clear if [[Digital Equipment Corporation|DEC]] ever sold that configuration.
+The MSV11-RA (M7358-A) holds 1 MByte when fully populated with 256K DRAM  [[integrated circuit|chips]]. The memory is arranged as 2 banks, each 16 data bits (1 [[PDP-11]] [[word]]) wide, with 2 additional bits for [[parity]] (1 per [[byte]]). In theory, it could support being half-populated (512 Kbytes), with only one bank; there is a jumper, W1, which seems to support this configuration, but no documentation for it. It is not clear if [[Digital Equipment Corporation|DEC]] ever sold that configuration.
 It is a [[QBUS#Variable address size|Q22]] card; it also supports block mode (with a maximum block size of 16. words, depending on the block's start [[address]]).
@@ Line 127: / Line 127: @@
 * ''MSV11-R User Guide'', EK-MSV1R-UG
-<!--* ''MSV11-R Field Maintenance Printset'' (MP-0 - not online) -->
+<!--* ''MSV11-R Field Maintenance Printset'' (MP-xxxx - not online) -->
 ==External links==

@@ Line 7: / Line 7: @@
 The MSV111-RA (M7358-A) holds 1 MByte when fully populated with 256K DRAM  [[integrated circuit|chips]]. The memory is arranged as 2 banks, each 16 data bits (1 [[PDP-11]] [[word]]) wide, with 2 additional bits for [[parity]] (1 per [[byte]]). In theory, it could support being half-populated (512 Kbytes), with only one bank; there is a jumper, W1, which seems to support this configuration, but no documentation for it. It is not clear if [[Digital Equipment Corporation|DEC]] ever sold that configuration.
-It is a [[QBUS#Variable address size|Q22]] card, and apparently supports block mode.
+It is a [[QBUS#Variable address size|Q22]] card; it also supports block mode (with a maximum block size of 16. words, depending on the block's start [[address]]).
 ==Configuration==
@@ Line 13: / Line 13: @@
 A single 8-position [[Dual Inline Package|DIP]] switch configures the card:
-* Switches S1-S2 sets bits 21-20 of the 22-bit starting [[address]];
+* Switches S1-S2 sets bits 21-20 of the board's 22-bit starting address;
 * DEC documentation asserts that switches S3-S4 must always be off; however they seem to be functional (although perhaps only for the single bank configuration), and set address bits 19-18;
 * Switches S5-S8 select the CSR address.

← Older revision		Revision as of 00:43, 14 December 2020
Line 136:		Line 136:

	[[Category: QBUS Memories]]		[[Category: QBUS Memories]]
−	[[Category: PMI ~~memories~~]]	+	[[Category: PMI Memories]]

← Older revision		Revision as of 23:47, 13 December 2020
Line 136:		Line 136:

	[[Category: QBUS Memories]]		[[Category: QBUS Memories]]
		+	[[Category: PMI memories]]

@@ Line 14: / Line 14: @@
 * Switches S1-S2 sets bits 21-20 of the 22-bit starting [[address]];
-* DEC documentation asserts that switches S3-S4 must always be off; however they seem to be functional (although perhaps only for the single bank configuration), and set bits 19-18;
+* DEC documentation asserts that switches S3-S4 must always be off; however they seem to be functional (although perhaps only for the single bank configuration), and set address bits 19-18;
 * Switches S5-S8 select the CSR address.
@@ Line 77: / Line 77: @@
 A copy of the engineering drawings for the MSV11-R has recently been discovered, in a set of [[PDP-11/84]] engineering drawings (see link below).
 As described above, each board has 2 banks in the array of DRAM chips; with 256K chips, each bank is thus 512KB. <!-- (Note that when writing data, the MSV11-R sends a 'write' [[signal]] to ''all'' the banks, and selects the one to ''actually'' use by use of the RAS signal. It's not certain why DEC did this, but since there is no explicit 'read' signal to the chip, and likely the outputs from all the banks are [[wire-OR]]'d together, use of RAS to select the desired bank works for read as well as write.)-->
-The chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the top). Bit 0 (value 1) of the even byte of the low bank is on the right hand edge of the top row of the array; bit 15 (value 0100000), the top bit of the odd byte, is toward the left hand side of the second row. The two parity bits are on the extreme left hand edge. The high bank is in the third and fourth rows down the board from the metal handle edge.<!-- The full table is:
+The chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the top). Bit 0 (value 1) of the even byte of the low bank is on the right hand edge of the top row of the array; bit 15 (value 0100000), the top bit of the odd byte, is toward the left hand side of the second row. The two parity bits are on the extreme left hand edge. The high bank is in the third and fourth rows down the board from the metal handle edge. The full bit<->chip table is:
 {| class="wikitable"
-! Bit !! Bank 0 !! Bank 1 !! Bank 2 !! Bank 3 !! Bank 4 !! Bank 5 !! Bank 6 !! Bank 7
+! Bit !! Bank 0 !! Bank 1
 |-
-| 01 || E197 || E196 || E195 || E194 || E193 || E192 || E191 || E190
+| 01 || E76 || E78
 |-
-| 02 || E189 || E188 || E187 || E186 || E185 || E184 || E183 || E182
+| 02 || E83 || E85
 |-
-| 04 || E180 || E179 || E178 || E177 || E176 || E175 || E174 || E173
+| 04 || E90 || E92
 |-
-| 10 || E172 || E171 || E170 || E170 || E169 || E168 || E167 || E166
+| 10 || E94 || E96
 |-
-| 20 || E164 || E163 || E162 || E161 || E160 || E159 || E158 || E157
+| 20 || E101 || E103
 |-
-| 40 || E155 || E154 || E153 || E152 || E151 || E150 || E149 || E148
+| 40 || E108 || E110
 |-
-| 100 || E147 || E146 || E145 || E144 || E143 || E142 || E141 || E140
+| 100 || E114 || E116
 |-
-| 200 || E139 || E138 || E137 || E136 || E135 || E134 || E133 || E132
+| 200 || E121 || E123
 |-
-| 400 || E114 || E113 || E112 || E111 || E110 || E109 || E108 || E107
+| 400 || E75 || E77
 |-
-| 1000 || E105 || E104 || E103 || E102 || E101 || E100 || E99 || E98
+| 1000 || E82 || E84
 |-
-| 2000 || E97 || E96 || E95 || E94 || E93 || E92 || E91 || E90
+| 2000 || E89 || E91
 |-
-| 4000 || E89 || E88 || E87 || E86 || E85 || E84 || E83 || E82
+| 4000 || E93 || E95
 |-
-| 10000 || E81 || E80 || E79 || E78 || E77 || E76 || E75 || E74
+| 10000 || E100 || E102
 |-
-| 20000 || E72 || E71 || E70 || E70 || E69 || E68 || E67 || E66
+| 20000 || E107 || E109
 |-
-| 40000 || E64 || E63 || E62 || E61 || E60 || E59 || E58 || E57
+| 40000 || E113 || E115
 |-
-| 100000 || E56 || E55 || E54 || E53 || E52 || E51 || E50 || E49
+| 100000 || E120 || E122
 |-
-| Low byte Parity || E
+| Low byte Parity || E128 || E130
 |-
-| High byte Parity || E
+| High byte Parity || E127 || E129
-|}-->
+|}
 <!-- ''Note:'' When a DRAM chip is removed, if the affected memory location is then read, that bit will be ''high'' (1), not ''low'' (0); the affected input (apparently separate pins for the low and high banks) must float to 1 when there is no DRAM chip present to drive the input. -->
 The following 256K DRAM chips have been observed to be used: MB81256-15 (Fujitsu).<!-- M5K4164ANP-15P (Micron Technologies), NEC D4164C211 (NEC Electronics). <!-- HM50256-15 (Hitachi), TMS4256-15NL (Texas Instruments)
-Note that some of these parts are 120 nsec parts, while others are 150 nsec; the faster parts do not seem to be necessary, or give any advantage. -->
+Note that some of these parts are 120 nsec parts, while others are 150 nsec; the faster parts do not seem to be necessary, or give any advantage.
 ==Further reading==

@@ Line 1: / Line 1: @@
 [[Image:MSV11-R.jpg|thumb|250px|right|MSV11-R card]]
-The '''MSV11-R''' (M7458) is a [[DEC card form factor|quad]]-height [[QBUS]] [[Dynamic RAM|DRAM]] [[main memory]] card. The MSV111-RA (M7358-A) holds 1 MByte when fully populated with 256K DRAMs  [[integrated circuit|chips]].<!--, or 2 Mbytes when half-populated (the only partially-filled configuration allowed). -->
+The '''MSV11-R''' (M7458) is a [[DEC card form factor|quad]]-height [[QBUS]]/[[Private Memory Interconnect|PMI]] [[Dynamic RAM|DRAM]] [[main memory]] card.
-The memory is arranged as 2 banks, each 16 data bits (1 [[PDP-11]] [[word]]) wide, with 2 additional bits for [[parity]] (1 per [[byte]]). It is a [[QBUS#Variable address size|Q22]] card; reportedly it is also a [[Private Memory Interconnect|PMI]] card. <!-- and support block mode. -->
+'''''NOTE:''''' As a PMI card, it uses the [[CD interconnect]]; it can therefore ''only'' be plugged into a [[QBUS#Backplanes|Q/CD backplane]]. Plugging an MSV11-R card into a regular [[QBUS#Backplanes|Q/Q backplane]] will '''damage''' the MSV11-R.
 ==Configuration==