MX15-B Memory Multiplexer - Revision history

Jnc: Correct docs for MX15-_B_ (different from -A

2022-11-30T22:35:23Z

Correct docs for MX15-_B_ (different from -A

← Older revision		Revision as of 22:35, 30 November 2022
Line 1:		Line 1:
	The '''MX15-B Memory ~~Bus~~ Multiplexer''' was part of the [[UNICHANNEL 15 System]], which allowed a [[PDP-11]] (usually a [[PDP-11/05]]) to act as a [[front end]] for a [[PDP-15]].		The '''MX15-B Memory Multiplexer''' was part of the [[UNICHANNEL 15 System]], which allowed a [[PDP-11]] (usually a [[PDP-11/05]]) to act as a [[front end]] for a [[PDP-15]].

	The MX15-B allowed the PDP-11 (both the [[Central Processing Unit\|CPU]], and [[Direct Memory Access\|DMA]] devices on the PDP-11's [[UNIBUS]]) access to ~~the~~ PDP-15's [[main memory]], and also allowed the PDP-15 access to the PDP-11's memory - i.e. ~~tuned~~ both memories into [[shared memory]].		The MX15-B allowed the PDP-11 (both the [[Central Processing Unit\|CPU]], and [[Direct Memory Access\|DMA]] devices on the PDP-11's [[UNIBUS]]) access to PDP-15 [[main memory]] attached to the MX15-B, and also allowed the PDP-15 CPU access to both the PDP-11's memory, and that PDP-15 memory - i.e. it turned both memories into [[shared memory]].

	Some DMA devices on the UNIBUS (such as the [[RK11 disk controller#RK11-E\|RK11-E]]) were able to do [[UNIBUS parity#18-bit width\|18-bit transfers]] over it; they used the two UNIBUS [[parity]] lines for the two extra data bits of the 18-bit PDP-15. The two extra bits were not used by the PDP-11 or its memory, but went straight through the MX15-B, directly to the PDP-15's memory.		Some DMA devices on the UNIBUS (such as the [[RK11 disk controller#RK11-E\|RK11-E]]) were able to do [[UNIBUS parity#18-bit width\|18-bit transfers]] over it; they used the two UNIBUS [[parity]] lines for the two extra data bits of the 18-bit PDP-15. The two extra bits were not used by the PDP-11 or its memory, but went straight through the MX15-B, directly to the PDP-15's memory.
Line 11:		Line 11:
	==External links==		==External links==

	* [http://bitsavers.org/pdf/dec/pdp15/~~hardware~~/DEC-15-~~H2XB~~-~~D_MX15_Aug71~~.pdf ~~MX15 Memory Bus Multiplexer~~ Maintenance Manual ~~Volume 1~~] (DEC-15-~~H2XB~~-D)		* [http://bitsavers.org/pdf/dec/pdp15/XVM/DEC-15-HUCMA-B-D_UC15_Nov73.pdf UNICHANNEL 15 System Maintenance Manual] (DEC-15-HUCMA-B-D) - the MX15-B is covered in detail in Chapter 4
	* [http://bitsavers.org/pdf/dec/pdp15/~~hardware~~/~~DEC-15-H2XB-D_MX15_EngrDrws_Sep71~~.pdf ~~MX15 Memory Bus Multiplexer Maintenance Manual Volume 2~~ - Engineering Drawings] ~~(DEC~~-15-~~H2XB~~-D)		* [http://bitsavers.org/pdf/dec/pdp15/XVM/UC15_schematics_Aug76.pdf UC15-0 Engineering Drawings] - the MX15-B is covered on pp. 18-44 of the PDF

	[[Category: PDP-15s]]		[[Category: PDP-15s]]
	[[Category: UNIBUS Machine Interfaces]]		[[Category: UNIBUS Machine Interfaces]]

Jnc: better cat

2022-11-28T12:47:08Z

better cat

← Older revision		Revision as of 12:47, 28 November 2022
Line 14:		Line 14:
	* [http://bitsavers.org/pdf/dec/pdp15/hardware/DEC-15-H2XB-D_MX15_EngrDrws_Sep71.pdf MX15 Memory Bus Multiplexer Maintenance Manual Volume 2 - Engineering Drawings] (DEC-15-H2XB-D)		* [http://bitsavers.org/pdf/dec/pdp15/hardware/DEC-15-H2XB-D_MX15_EngrDrws_Sep71.pdf MX15 Memory Bus Multiplexer Maintenance Manual Volume 2 - Engineering Drawings] (DEC-15-H2XB-D)

	[[Category: ~~DEC Processors~~]]		[[Category: PDP-15s]]
	[[Category: UNIBUS Machine Interfaces]]		[[Category: UNIBUS Machine Interfaces]]

Jnc: /* External links */ +manual, EngDrwng

2022-11-26T00:21:27Z

External links: +manual, EngDrwng

← Older revision		Revision as of 00:21, 26 November 2022
Line 1:		Line 1:
	The '''MX15-B Memory Multiplexer''' was part of the [[UNICHANNEL 15 System]], which allowed a [[PDP-11]] (usually a [[PDP-11/05]]) to act as a [[front end]] for a [[PDP-15]].		The '''MX15-B Memory Bus Multiplexer''' was part of the [[UNICHANNEL 15 System]], which allowed a [[PDP-11]] (usually a [[PDP-11/05]]) to act as a [[front end]] for a [[PDP-15]].

	The MX15-B allowed the PDP-11 (both the [[Central Processing Unit\|CPU]], and [[Direct Memory Access\|DMA]] devices on the PDP-11's [[UNIBUS]]) access to the PDP-15's [[main memory]], and also allowed the PDP-15 access to the PDP-11's memory - i.e. tuned both memories into [[shared memory]].		The MX15-B allowed the PDP-11 (both the [[Central Processing Unit\|CPU]], and [[Direct Memory Access\|DMA]] devices on the PDP-11's [[UNIBUS]]) access to the PDP-15's [[main memory]], and also allowed the PDP-15 access to the PDP-11's memory - i.e. tuned both memories into [[shared memory]].
Line 8:		Line 8:

	Memory addresses in the PDP-11 (which uses byte addressing) were converted to PDP-15 word addressing by dropping the low bit, and conversely for transfers in the other direction. It also converted DATIP and DATOB type UNIBUS cycles (which have no exact equivalents in the PDP-15's memory system) to PDP-15 memory operations with the same effect.		Memory addresses in the PDP-11 (which uses byte addressing) were converted to PDP-15 word addressing by dropping the low bit, and conversely for transfers in the other direction. It also converted DATIP and DATOB type UNIBUS cycles (which have no exact equivalents in the PDP-15's memory system) to PDP-15 memory operations with the same effect.

			==External links==

			* [http://bitsavers.org/pdf/dec/pdp15/hardware/DEC-15-H2XB-D_MX15_Aug71.pdf MX15 Memory Bus Multiplexer Maintenance Manual Volume 1] (DEC-15-H2XB-D)
			* [http://bitsavers.org/pdf/dec/pdp15/hardware/DEC-15-H2XB-D_MX15_EngrDrws_Sep71.pdf MX15 Memory Bus Multiplexer Maintenance Manual Volume 2 - Engineering Drawings] (DEC-15-H2XB-D)

	[[Category: DEC Processors]]		[[Category: DEC Processors]]
	[[Category: UNIBUS Machine Interfaces]]		[[Category: UNIBUS Machine Interfaces]]

Jnc: link new article

2022-04-29T13:43:49Z

link new article

← Older revision		Revision as of 13:43, 29 April 2022
Line 1:		Line 1:
	The '''MX15-B Memory Multiplexer''' was part of the [[UNICHANNEL 15 System]], which allowed a [[PDP-11]] (usually a [[PDP-11/05]]) to act as a [[front end]] for a [[PDP-15]].		The '''MX15-B Memory Multiplexer''' was part of the [[UNICHANNEL 15 System]], which allowed a [[PDP-11]] (usually a [[PDP-11/05]]) to act as a [[front end]] for a [[PDP-15]].

	The MX15-B allowed the PDP-11 (both the [[Central Processing Unit\|CPU]], and [[Direct Memory Access\|DMA]] devices on the PDP-11's [[UNIBUS]]) access to the PDP-15's [[main memory]], and also allowed the PDP-15 access to the PDP-11's memory.		The MX15-B allowed the PDP-11 (both the [[Central Processing Unit\|CPU]], and [[Direct Memory Access\|DMA]] devices on the PDP-11's [[UNIBUS]]) access to the PDP-15's [[main memory]], and also allowed the PDP-15 access to the PDP-11's memory - i.e. tuned both memories into [[shared memory]].

	Some DMA devices on the UNIBUS (such as the [[RK11 disk controller#RK11-E\|RK11-E]]) were able to do [[UNIBUS parity#18-bit width\|18-bit transfers]] over it; they used the two UNIBUS [[parity]] lines for the two extra data bits of the 18-bit PDP-15. The two extra bits were not used by the PDP-11 or its memory, but went straight through the MX15-B, directly to the PDP-15's memory.		Some DMA devices on the UNIBUS (such as the [[RK11 disk controller#RK11-E\|RK11-E]]) were able to do [[UNIBUS parity#18-bit width\|18-bit transfers]] over it; they used the two UNIBUS [[parity]] lines for the two extra data bits of the 18-bit PDP-15. The two extra bits were not used by the PDP-11 or its memory, but went straight through the MX15-B, directly to the PDP-15's memory.

Jnc: new better cat

2021-12-11T01:37:22Z

new better cat

← Older revision		Revision as of 01:37, 11 December 2021
Line 10:		Line 10:

	[[Category: DEC Processors]]		[[Category: DEC Processors]]
	[[Category: ~~PDP-11 Processors~~]]		[[Category: UNIBUS Machine Interfaces]]

Jnc: link 18-bit mode

2019-12-03T14:49:12Z

link 18-bit mode

← Older revision		Revision as of 14:49, 3 December 2019
Line 3:		Line 3:
	The MX15-B allowed the PDP-11 (both the [[Central Processing Unit\|CPU]], and [[Direct Memory Access\|DMA]] devices on the PDP-11's [[UNIBUS]]) access to the PDP-15's [[main memory]], and also allowed the PDP-15 access to the PDP-11's memory.		The MX15-B allowed the PDP-11 (both the [[Central Processing Unit\|CPU]], and [[Direct Memory Access\|DMA]] devices on the PDP-11's [[UNIBUS]]) access to the PDP-15's [[main memory]], and also allowed the PDP-15 access to the PDP-11's memory.

	Some DMA devices on the UNIBUS (such as the [[RK11 disk controller#RK11-E\|RK11-E]]) were able to do 18-bit transfers over it; they used the two UNIBUS parity lines for the two extra data bits of the 18-bit PDP-15. The two extra bits were not used by the PDP-11 or its memory, but went straight through the MX15-B, directly to the PDP-15's memory.		Some DMA devices on the UNIBUS (such as the [[RK11 disk controller#RK11-E\|RK11-E]]) were able to do [[UNIBUS parity#18-bit width\|18-bit transfers]] over it; they used the two UNIBUS [[parity]] lines for the two extra data bits of the 18-bit PDP-15. The two extra bits were not used by the PDP-11 or its memory, but went straight through the MX15-B, directly to the PDP-15's memory.

	The MX15-B included an [[arbiter]], so that when the PDP-15 and PDP-11 (both of which are [[asynchronous]]) tried to interact with memory at the same time, a choice was made; the PDP-15 was given priority.		The MX15-B included an [[arbiter]], so that when the PDP-15 and PDP-11 (both of which are [[asynchronous]]) tried to interact with memory at the same time, a choice was made; the PDP-15 was given priority.

	Memory addresses in the PDP-11 (which uses byte addressing) were converted to PDP-15 word addressing by dropping the low ~~bits~~, and conversely for transfers in the other direction. It also converted DATIP and DATOB type UNIBUS cycles (which have no exact equivalents in the PDP-15's memory system) to PDP-15 memory operations with the same effect.		Memory addresses in the PDP-11 (which uses byte addressing) were converted to PDP-15 word addressing by dropping the low bit, and conversely for transfers in the other direction. It also converted DATIP and DATOB type UNIBUS cycles (which have no exact equivalents in the PDP-15's memory system) to PDP-15 memory operations with the same effect.

	[[Category: DEC Processors]]		[[Category: DEC Processors]]
	[[Category: PDP-11 Processors]]		[[Category: PDP-11 Processors]]

Jnc: +cats

2018-12-16T22:00:59Z

+cats

← Older revision		Revision as of 22:00, 16 December 2018
Line 8:		Line 8:

	Memory addresses in the PDP-11 (which uses byte addressing) were converted to PDP-15 word addressing by dropping the low bits, and conversely for transfers in the other direction. It also converted DATIP and DATOB type UNIBUS cycles (which have no exact equivalents in the PDP-15's memory system) to PDP-15 memory operations with the same effect.		Memory addresses in the PDP-11 (which uses byte addressing) were converted to PDP-15 word addressing by dropping the low bits, and conversely for transfers in the other direction. It also converted DATIP and DATOB type UNIBUS cycles (which have no exact equivalents in the PDP-15's memory system) to PDP-15 memory operations with the same effect.

			[[Category: DEC Processors]]
			[[Category: PDP-11 Processors]]

Jnc: Typos, links, clarify

2017-12-11T18:24:12Z

Typos, links, clarify

← Older revision		Revision as of 18:24, 11 December 2017
Line 1:		Line 1:
	The '''MX15-B Memory Multiplexer''' was part of the [[UNICHANNEL 15 System]], which allowed a [[PDP-11]] (usually a [[PDP-11/05]] to act as a [[front end]] for a [[PDP-15]].		The '''MX15-B Memory Multiplexer''' was part of the [[UNICHANNEL 15 System]], which allowed a [[PDP-11]] (usually a [[PDP-11/05]]) to act as a [[front end]] for a [[PDP-15]].

	The MX15-B allowed the PDP-11 (both the CPU, and [[Direct Memory Access\|DMA]] devices on the PDP-11's [[UNIBUS]]) access to the PDP-15's [[main memory]], and also allowed the PDP-15 access to the PDP-11's memory.		The MX15-B allowed the PDP-11 (both the [[Central Processing Unit\|CPU]], and [[Direct Memory Access\|DMA]] devices on the PDP-11's [[UNIBUS]]) access to the PDP-15's [[main memory]], and also allowed the PDP-15 access to the PDP-11's memory.

	Some DMA devices on the UNIBUS (such as the [[RK11 disk controller#RK11-E\|RK11-E]]) were able to do 18-bit transfers; they used the two UNIBUS parity lines for the two extra data bits of the 18-bit PDP-15. The two extra bits were not used by the PDP-11 or its memory, but went straight through the MX15-B, directly to the PDP-15's memory.		Some DMA devices on the UNIBUS (such as the [[RK11 disk controller#RK11-E\|RK11-E]]) were able to do 18-bit transfers over it; they used the two UNIBUS parity lines for the two extra data bits of the 18-bit PDP-15. The two extra bits were not used by the PDP-11 or its memory, but went straight through the MX15-B, directly to the PDP-15's memory.

	It included an [[arbiter]], so that when the PDP-15 and PDP-11 (both of which are [[asynchronous]]) tried to interact with memory at the same time, a choice was made; the PDP-15 was given priority.		The MX15-B included an [[arbiter]], so that when the PDP-15 and PDP-11 (both of which are [[asynchronous]]) tried to interact with memory at the same time, a choice was made; the PDP-15 was given priority.

	Memory addresses in the PDP-11 (which uses byte addressing) were converted to PDP-15 (word addressing) by dropping the low bits, and ~~similarly~~ for transfers in the other direction. It also converted DATIP and DATOB type UNIBUS cycles (which have no exact equivalents in the PDP-15's memory system) to PDP-15 memory operations with the same effect.		Memory addresses in the PDP-11 (which uses byte addressing) were converted to PDP-15 word addressing by dropping the low bits, and conversely for transfers in the other direction. It also converted DATIP and DATOB type UNIBUS cycles (which have no exact equivalents in the PDP-15's memory system) to PDP-15 memory operations with the same effect.

Jnc: A decent description

2017-12-10T14:01:47Z

A decent description

New page

The '''MX15-B Memory Multiplexer''' was part of the [[UNICHANNEL 15 System]], which allowed a [[PDP-11]] (usually a [[PDP-11/05]] to act as a [[front end]] for a [[PDP-15]].

The MX15-B allowed the PDP-11 (both the CPU, and [[Direct Memory Access|DMA]] devices on the PDP-11's [[UNIBUS]]) access to the PDP-15's [[main memory]], and also allowed the PDP-15 access to the PDP-11's memory.

Some DMA devices on the UNIBUS (such as the [[RK11 disk controller#RK11-E|RK11-E]]) were able to do 18-bit transfers; they used the two UNIBUS parity lines for the two extra data bits of the 18-bit PDP-15. The two extra bits were not used by the PDP-11 or its memory, but went straight through the MX15-B, directly to the PDP-15's memory.

It included an [[arbiter]], so that when the PDP-15 and PDP-11 (both of which are [[asynchronous]]) tried to interact with memory at the same time, a choice was made; the PDP-15 was given priority.

Memory addresses in the PDP-11 (which uses byte addressing) were converted to PDP-15 (word addressing) by dropping the low bits, and similarly for transfers in the other direction. It also converted DATIP and DATOB type UNIBUS cycles (which have no exact equivalents in the PDP-15's memory system) to PDP-15 memory operations with the same effect.