Memory interleaving - Revision history

Jnc: Jnc moved page Interleaving to Memory interleaving: Eventually the redir will be turned into a dab

2023-07-29T21:12:11Z

Jnc moved page Interleaving to Memory interleaving: Eventually the redir will be turned into a dab

Jnc: Oh, now I understand what I wrote before - put it back, with some extra explanation

2019-03-21T21:36:58Z

Oh, now I understand what I wrote before - put it back, with some extra explanation

Jnc: typo

2019-03-21T19:08:29Z

typo

Jnc: Exlpain briefly why core has a large access/cycle difference, other improvements

2019-03-21T14:39:14Z

Exlpain briefly why core has a large access/cycle difference, other improvements

Jnc: +cat

2018-12-15T14:34:47Z

+cat

Jnc: Correct cat

2018-10-19T12:23:17Z

Correct cat

Jnc: A decent start

2018-07-14T12:38:56Z

A decent start

New page

'''Interleaving''' is a technique for speeding up access to sequential [[main memory]] [[address]]es (e.g. by the [[Central Processing Unit|CPU]] as it executes a [[program]]) for memories which have a [[cycle time]] which is significantly longer than their [[access time]], such as [[core memory]].

It consists of assigning sequential addresses to different memory units; so that a reference to [[word]] A goes to one bank, and a following reference to word A+1 goes to the other. This is called 'two-way interleaving', but it was possible to extend the technique; e.g. the [[KL10]] could use four-way interleaving.

The implementation was fairly simple; switches were provided which exchanged two of the bits on the address [[bus]] as they were fed into each memory unit; the two bits would be the low bit of the word address (since some memories were [[byte]] addressed), and the bit just about the highest bit of the memory's local address. Thus, sequential addresses (on the bus) would alternate between memory units.

This did mean that sequential words in the actual memory would be in different blocks of the [[address space]], but keeping the words in order would have required a lot more wiring (to effectively shift the entire local part of the address down one bit). It was much simpler to simply accept the unusual order (which the CPU could not see, anyway).

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 It consists of assigning sequential addresses to different memory units; so that a reference to [[word]] A goes to one bank, and a following reference to word A+1 goes to the other. It was not unknown for interleaving to decrease the access time for a second word by up to 50%, a very significant savings. This is called 'two-way interleaving', but it was possible to extend the technique; e.g. the [[KL10]] could use four-way interleaving.
-The implementation was fairly simple, and thus has a large cost/benefit ratio (especially in a oeriod where individual [[transistor]]s had significant cost). Switches were provided which exchanged two of the bits on the address [[bus]] as they were fed into each memory unit; the two bits would be the low bit of the word address (since some memories were [[byte]] addressed), and the bit just above the highest bit of the memory's local address. Thus, sequential addresses (on the bus) would alternate between memory units.
+The implementation was fairly simple, and thus has a large cost/benefit ratio (especially in a period where individual [[transistor]]s, needed to do anything complex, had significant cost). Switches were provided which exchanged two of the bits on the address [[bus]] as they were fed into each memory unit; the two bits would be the low bit of the word address (since some memories were [[byte]] addressed), and the bit just above the highest bit of the memory's internal address. Thus, sequential addresses (on the bus) would alternate between memory units.
-This did mean that sequential words in the actual memory would not be sequential in the [[address space]], but keeping the words in order would vitiate the whole point of interleaving (to direct sequential requests to different memory units); it was much simpler to simply accept the unusual order (which the CPU could not see, anyway).
+Use of this method did mean that sequential words in the actual memory would be in different blocks of the [[address space]] (since the high bit in the bus address. which selected the block, would be the low address bit ''inside'' the memory), but keeping the words in order would have required a lot more wiring (to effectively shift the entire local part of the address down one bit). It was much simpler to simply accept the unusual order (which the CPU could not see, anyway).
 Also, the simple technique of exchanging address bits only works with two (or more) memories of equal size.

@@ Line 3: / Line 3: @@
 It consists of assigning sequential addresses to different memory units; so that a reference to [[word]] A goes to one bank, and a following reference to word A+1 goes to the other. It was not unknown for interleaving to decrease the access time for a second word by up to 50%, a very significant savings. This is called 'two-way interleaving', but it was possible to extend the technique; e.g. the [[KL10]] could use four-way interleaving.
-The implementation was fairly simple, and thus has a large cost/benefit ratio (especially in a oeriod where individual [[transistor]]s had significant cost). Switches were provided which exchanged two of the bits on the address [[bus]] as they were fed into each memory unit; the two bits would be the low bit of the word address (since some memories were [[byte]] addressed), and the bit just about the highest bit of the memory's local address. Thus, sequential addresses (on the bus) would alternate between memory units.
+The implementation was fairly simple, and thus has a large cost/benefit ratio (especially in a oeriod where individual [[transistor]]s had significant cost). Switches were provided which exchanged two of the bits on the address [[bus]] as they were fed into each memory unit; the two bits would be the low bit of the word address (since some memories were [[byte]] addressed), and the bit just above the highest bit of the memory's local address. Thus, sequential addresses (on the bus) would alternate between memory units.
 This did mean that sequential words in the actual memory would not be sequential in the [[address space]], but keeping the words in order would vitiate the whole point of interleaving (to direct sequential requests to different memory units); it was much simpler to simply accept the unusual order (which the CPU could not see, anyway).

@@ Line 1: / Line 1: @@
-'''Interleaving''' is a technique for speeding up access to sequential [[main memory]] [[address]]es (e.g. by the [[Central Processing Unit|CPU]] as it executes a [[program]]) for memories which have a [[cycle time]] which is significantly longer than their [[access time]], such as [[core memory]].
+'''Interleaving''' is a technique for speeding up access to sequential [[main memory]] [[address]]es (e.g. by the [[Central Processing Unit|CPU]] as it executes a [[program]]), for memories which have a [[cycle time]] which is significantly longer than their [[access time]]. (The classic example is [[core memory]], which inherently has a much longer cycle time since it has destructive readout; the data has to be written back before a read cycle can complete.)
-It consists of assigning sequential addresses to different memory units; so that a reference to [[word]] A goes to one bank, and a following reference to word A+1 goes to the other. This is called 'two-way interleaving', but it was possible to extend the technique; e.g. the [[KL10]] could use four-way interleaving.
+It consists of assigning sequential addresses to different memory units; so that a reference to [[word]] A goes to one bank, and a following reference to word A+1 goes to the other. It was not unknown for interleaving to decrease the access time for a second word by up to 50%, a very significant savings. This is called 'two-way interleaving', but it was possible to extend the technique; e.g. the [[KL10]] could use four-way interleaving.
-The implementation was fairly simple; switches were provided which exchanged two of the bits on the address [[bus]] as they were fed into each memory unit; the two bits would be the low bit of the word address (since some memories were [[byte]] addressed), and the bit just about the highest bit of the memory's local address. Thus, sequential addresses (on the bus) would alternate between memory units.
+The implementation was fairly simple, and thus has a large cost/benefit ratio (especially in a oeriod where individual [[transistor]]s had significant cost). Switches were provided which exchanged two of the bits on the address [[bus]] as they were fed into each memory unit; the two bits would be the low bit of the word address (since some memories were [[byte]] addressed), and the bit just about the highest bit of the memory's local address. Thus, sequential addresses (on the bus) would alternate between memory units.
-This did mean that sequential words in the actual memory would be in different blocks of the [[address space]], but keeping the words in order would have required a lot more wiring (to effectively shift the entire local part of the address down one bit). It was much simpler to simply accept the unusual order (which the CPU could not see, anyway).
+This did mean that sequential words in the actual memory would not be sequential in the [[address space]], but keeping the words in order would vitiate the whole point of interleaving (to direct sequential requests to different memory units); it was much simpler to simply accept the unusual order (which the CPU could not see, anyway).
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 [[Category: Memory Basics]]

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	This did mean that sequential words in the actual memory would be in different blocks of the [[address space]], but keeping the words in order would have required a lot more wiring (to effectively shift the entire local part of the address down one bit). It was much simpler to simply accept the unusual order (which the CPU could not see, anyway).		This did mean that sequential words in the actual memory would be in different blocks of the [[address space]], but keeping the words in order would have required a lot more wiring (to effectively shift the entire local part of the address down one bit). It was much simpler to simply accept the unusual order (which the CPU could not see, anyway).

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← Older revision	Revision as of 21:12, 29 July 2023
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